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Semiconductor chip

A semiconductor and wafer technology, applied in the field of semiconductor integrated circuit devices, can solve the problems affecting the reliability of integrated circuit chips, interface delamination, etc.

Inactive Publication Date: 2008-07-30
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] During wafer dicing, since the surface of the wafer is subject to stress due to the use of mechanical cutters to grind the wafer, it is found that interfacial delamination is formed at the interface between dielectric materials with low dielectric constant during or after wafer dicing phenomenon, which affects the reliability of integrated circuit chips

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  • Semiconductor chip
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Embodiment Construction

[0019] The invention relates to the manufacture of semiconductor integrated circuit chips, in particular to the application of means capable of effectively blocking the delamination phenomenon of the dielectric layer interface caused by wafer cutting. As mentioned above, the interfacial delamination phenomenon of the dielectric layer occurs in the dielectric material with low dielectric constant, which may be caused during or after the wafer dicing process. Before the wafer is cut, there are many crystal squares or chips on the wafer, but at the four corners of each crystal square or chip, it is unexpectedly found that the delamination phenomenon of the dielectric layer interface is the most serious, and the dielectric layer interface Delamination goes deeper into the die or the central circuit area of ​​the chip, even if its periphery is protected by die seal rings or single crack barrier trenches.

[0020] The reason for the most serious delamination of the dielectric layer ...

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Abstract

The present invention discloses semiconductor chip. It features including plurality of integrated circuit chip area surrounded by cut line, cutting integrated circuit chip, each chip having four corners, protective layer simultaneously covering aforementioned integrated circuit chip area and cut line, first groove being etched penetrating aforementioned protective layer, then at least etching to dielectric layer and only arranged four corner of integrated circuit chip, second groove etching penetrating aforementioned protective layer configured on position near by aforementioned first groove, and protecting seal ring structure located between integrated circuit chip and first groove.

Description

technical field [0001] The invention relates to semiconductor integrated circuit devices, in particular to the field of manufacturing semiconductor integrated circuit chips, and relates to the application of a means capable of effectively blocking the delamination phenomenon of the dielectric layer interface caused by wafer cutting. Background technique [0002] With the miniaturization of semiconductor devices such as transistors, the efficiency and density of semiconductor integrated circuits are also greatly improved. When the manufacturing level of semiconductor integrated circuits reaches the technical level of sub-micron or nanometer, the resistance-capacitance delay becomes the bottleneck of whether the performance of the circuit can be further improved. The resistance-capacitance delay problem can be improved by reducing the line resistance of the metal interconnection line or the capacitance of the ground dielectric layer. Among them, in terms of reducing the line ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/78H01L21/301
Inventor 林宗辉刘洪民饶瑞孟张文通陈国明何凯光
Owner UNITED MICROELECTRONICS CORP