Data drive circuit, liquid crystal display panel, liquid crystal display module and display

Abstract

A data driving circuit used on film transistor liquid crystal display is prepared as switching off N1 numbers of channel outputs including multiplexer and displacement register, receiving level initial signal and at least one control signal by multiplexer and using said control signal to decide signal output of output end on multiplexer, receiving frequency signal and said output signal as well as outputting initial pulse signal by displacement register and using the first image data outputted by the first channel to decide which output end is used to output initial signal according to said output signal.

Description

technical field [0001] The present invention relates to a thin film transistor liquid crystal display, and in particular to its data driving circuit. Background technique [0002] Such as Figure 1A As shown, in some traditional digital applications, the resolution of a thin film transistor liquid crystal display (TFT-LCD) is 800RGB×480, which requires 5 480-channel data drive circuit chips. Since the number of screen horizontal channels is 800×3, It is exactly equal to the total number of channels that five 480-channel data drive circuit chips can provide. However, based on the consideration of cost reduction, the number of data drive circuit chips will be reduced from 5 to 3 as far as possible, and the number of channels of the data drive circuit chip needs to be changed to 800 channels. However, 800 is not a multiple of 3, and in the data drive circuit chip In terms of design, RGB is regarded as an inseparable unit. Therefore, 800 channels are not feasible in the design ...

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Problems solved by technology

[0003] However, when the design of the data driving circuit chip is 804 channels, the existing timing control chip cannot be used

like Figure 1B As shown, the 12 channels of one of the data drive circuit chips are not used, and it cannot be applied to the function that requires left-right inversion, and the timing control chip needs to be modified, and a first-in-first-out (FIFO) circuit is required After the data is latched (latch), the data is thrown out

Figure 1C Another situation is shown, in which 6 channels of the data drive circuit chips on the left and right sides are not used. This kind of left-right symmetrical layout is conducive to the application of left-right inversion, but the existing timing control chips still cannot provide corresponding support

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