Storage controller and control method

Abstract

The present invention discloses memory controller and control method, referring to storage technology in IP network equipment. It contains command resolving and initializing module, address and control interface module, read-write data path module and read-write data interface module, which are respectively interconnected between user application layer and memory; time division multiplexing control module connected with command resolving and initializing module; first in first out data processing module connected with read-write data path module. The present invention adopts time division multiplexing principle, dividing each time slice into number of time slot, distributing each memory block read write operation to relevant time slot, and ensuring twice consecutive access time interval to same memory block greater than or equal to tRC time, raising memory read-write data efficiency. The present invention processes data in memory according to first in first out mode, raising memory interface data access efficiency.

Description

[technical field] [0001] The invention relates to the technical field of storage in IP network equipment, in particular to a storage controller and a control method. [Background technique] [0002] With the development of IP networks, the data traffic transmitted by IP networks is increasing. Due to the sudden nature of IP network data traffic, more and more large-capacity, high-data-flow memories are used in IP network devices, such as QDR SSRAM (Quad Data Rate Synchronous Static Random Access Memory, Quad Data Rate Synchronous Static Random Access Memory), RLDRAM (Reduced Latency Dynamic Random Access Memory low-latency dynamic random access memory), DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory double data rate synchronous dynamic random access memory), SDRAM (Synchronous Dynamic Random Access Memory synchronous dynamic random access memory) and FCRAM (Fast Cycle Random Access Memory fast cycle dynamic memory). Since QDR SSRAM has a relatively sma...

AI Technical Summary

Problems solved by technology

This wastes the access data bandwidth of the memory during the period of tRC, thereby reducing the read and write efficiency of the memory.

Images