Dual-voltage three-state buffer circuit

Abstract

The invention provides a double-voltage three-state buffer circuit, which includes a three-state logic control unit, a level shifter, and a post-driver circuit. The tri-state logic control unit operates at a low supply voltage. The level shifter receives one or more input signals from the tri-state logic control unit, and operates with the output control circuit to control two differential output terminals of the level shifter. The post-driver circuit has a PMOS transistor and an NMOS transistor connected in series, and is driven by the two differential output terminals of the level shifter. Among them, the level shifter, the output control circuit, and the post-driver circuit operate at a high supply voltage. When the tri-state logic control unit generates multiple input signals to place the post-driver circuit in a high-impedance state, the output control circuit operates with the level shifter to turn off the PMOS and NMOS transistors to isolate the level shifter from the high supply Voltage.

Description

technical field [0001] The present invention relates to an integrated circuit, and in particular to an improved design of a dual-voltage tri-state buffer circuit using a tri-state level shifter. Background technique [0002] The existing dual-voltage tri-state buffer includes a two-level shifter for controlling a post driver circuit, and it is composed of PMOS and NMOS transistors. The two-level shifter converts lower voltage signals into higher voltage signals. The post-driver circuit determines the output of the entire circuit by deciding which transistors are on or off. However, since the driving of the PMOS transistor is slower than that of the NMOS transistor, the time required to turn on or off the PMOS and NMOS transistors is different. Since different input signals may establish different paths for signal transmission, and some paths may take more time, therefore, the time required for each level shifter to output signals is also different. According to these timi...

AI Technical Summary

Problems solved by technology

[0007] Although buffer 100 reduces post-driver crossover current and uses two-level shifters 102 and 104 to convert low-level voltages to high-level voltages, due to timing issues, the inverters driving post-driver transistors 112 and 114 Ratio is too unstable

In addition, level shifters 102 and 104 and inverters 156 and 158 increase power consumption and circuit layout area

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