Chip testing mechanism and related method

Abstract

The related chip testing method comprises: building inner loop in interface circuit of high-speed bus, sending information for I / O testing, and receiving the information by former inner loop to validate the chip I / O function and time sequence. This invention can save cost greatly and fit to take full-function I / O testing even in wafer stage.

Description

technical field [0001] The invention relates to a chip testing mechanism and a related method, in particular to a chip testing mechanism and a related method capable of being connected to a high-speed bus at low cost. Background technique [0002] In the electronic system, different electronic devices exchange information with each other through the bus, so that the electronic devices can coordinate operations and integrate their respective functions to complete the overall function of the electronic system. For example, in a computer system, the central processing unit is bridged to other peripheral devices (such as hard disk drives, optical drives, graphics accelerator cards, etc.) The interconnection with the bus enables the above-mentioned electronic devices to operate in an integrated manner. Of course, in the modern information society that emphasizes efficiency, the performance requirements for electronic systems are also increasing. In order to improve the overall ...

AI Technical Summary

Problems solved by technology

However, the external high-frequency tester is very expensive, so the production and manufacturing costs of electronic devices will remain high

For example, to test a chipset with a super-speed transmission bus, its tester needs to be able to handle high-frequency signals of 2GHz (because the super-speed transmission bus transmits data at 2GHz), and the cost of this high-frequency tester is very high

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