Chip packaging structure and manufacturing method therefor

Abstract

The present invention relates to a manufacturing method for the wafer encapsulation structure, and includes the following steps: firstly, a circuitry substrate with a first surface, a second surface and a through-hole connected with the two surfaces are provided. Secondly, a wafer with an active surface and a plurality of welding washers arranged on the active surface are provided. Thirdly, the wafer is fixed on the circuitry substrate, the second surface is face to face with the active surface, and the through-hole exposes the welding washers. Fourthly, a plurality of welding lines passed the through-hole and connected electrically with the welding washers and the first surface are formed. Fifthly, a film layer with one opening hole is formed on the first surface. The opening hole exposes the welding lines, the welding washers and the through-hole and a part of the first surface. Sixthly, a colloid is formed inside the opening hole and the through-hole to pack a part of the active surface, the welding lines and a part of the first surface. Lastly, the film layer is removed. Thereby the colloid overflow phenomenon can be mended, and the manufacturing cost can be reduced.

Description

Technical field [0001] The invention relates to a semiconductor element and a manufacturing method thereof, in particular to a chip packaging structure and a manufacturing method thereof. Background technique [0002] In the semiconductor industry, the production of integrated circuits (IC) can be divided into three stages: IC design, IC process, and IC package. [0003] In the production of integrated circuits, a chip is completed through the steps of wafer production, integrated circuit formation, and wafer sawing. The wafer has an active surface, which generally refers to the surface of the wafer with active components. After the integrated circuit inside the wafer is completed, the active surface of the wafer is further equipped with a plurality of bonding pads, so that the final chip formed by wafer dicing can be electrically connected to an external through these bonding pads. Carrier (carrier). The carrier is, for example, a lead frame or a package substrate. The chip can ...

AI Technical Summary

Problems solved by technology

Therefore, when performing the sealing process, the upper and lower parts of the molds used for the chip packaging structure 100 of different sizes have inconsistent shapes, which will increase the cost of mold making.

In addition, during the encapsulation process, sometimes glue overflow (flash) phenomenon occurs to contaminate the first surface 112 of the circuit substrate 110

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