Method for manufacturing single level polysilicon electric removal and programmable read only memory cell

Abstract

A method for forming a depleted single-layer polysilicon electrically erasable programmable read-only memory unit. The method includes: providing a substrate with a floating region and a control region, forming an isolated deep well region and a deep well region in the substrate of the floating region and the control region respectively, wherein the isolated deep well region It has the same conductivity type as the deep well region. After that, a well region and an isolated well region are respectively formed in the isolated deep well region and in the substrate between the isolated deep well region and the deep well region. A depletion doping region and a memory unit implantation region are respectively formed in the well region and the deep well region. A floating gate structure straddling the floating region and the control region is formed on the substrate, wherein the floating gate structure respectively exposes a part of the depletion doped region and a part of the memory unit implantation region. Finally, a doping process is performed to form a source / drain region and a heavily doped region in the exposed part of the depleted doped region and the exposed part of the memory unit implanted region respectively.

Description

technical field [0001] The present invention relates to a non-volatile memory cell, its forming method and operation method, and in particular to a single-poly EEPROM cell (single-poly EEPROM cell), its manufacturing method and its operation method. Background technique [0002] With the popularity of consumer electronic products, non-volatile memory (non-volatile memory), which can retain stored data and data even when the power is turned off, is widely used in various electronic devices , including multimedia or portable multimedia application devices, such as digital cameras, walkmans, or portable phones. The integration process of non-volatile memory with other devices, such as CMOS, logic device, high voltage device and low voltage device, has become one of the current manufacturing development trends. [0003] The existing Electrically Erasable Programmable Read-Only Memory (EEPROM) is a non-volatile memory. A general EEPROM cell has two stacked gates, including a f...

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Problems solved by technology

[0004] Since the existing EEPROM has two stacked polysilicon gates, its step height is greater than that of other single-layer polysilicon devices, so the EEPROM is added. Difficulties in integrating process with other components

In addition, in order to integrate the two-layer polysilicon EEPROM and the single-layer polysilicon device, more photomasks are required and the process steps are more complicated.

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