Multiple chip packaged conductor frame, its producing method and its package structure

Abstract

A lead frame for multi-chip packaging and its packaging structure. The lead frame includes a chip seat and a plurality of guide pins. A dielectric layer is formed on the lower surface of the chip seat. The chip seat is etched to form at least one center with a bonding area. The relay conductor is arranged in the opening of the chip holder, the chip holder and the relay conductor are located on the same surface of the dielectric layer, and an electrical insulation layer is formed on the relay conductor and exposes the bonding area. The manufacturing method of the lead frame includes: providing a lead frame, which is provided with a chip holder including upper and lower surfaces and openings and a plurality of guide pins; forming a dielectric layer on the lower surface of the chip holder; etching the chip holder , so that at least one relay conductor is formed, the relay conductor is electrically insulatingly attached to the dielectric layer and arranged in the opening, the relay conductor has a bonding area; an electrical insulation layer is formed on the chip holder The relay conductor, and the electrical insulation layer exposes the junction area of ​​the relay conductor. The invention can make the chip or the passive element electrically connect with the lead pin through the relay conductor.

Description

Technical field [0001] The present invention relates to a lead frame, in particular to a lead frame of a multi-chip package and a manufacturing method thereof, and a multi-chip package structure containing the lead frame. Background technique [0002] Multi-chip package (MCP) is a packaging technology that has received more and more attention. It integrates multiple chips of different or the same type, and even passive components, into a semiconductor package structure to achieve The characteristic of complete function or high capacity, but therefore its electrical conduction path will become more complicated, so the commonly used multi-chip package chip carrier is a multilayer circuit substrate, in order to reduce packaging costs, some people try to The low-cost lead frame replaces the multilayer circuit board. [0003] Taiwan Patent Publication No. 428875 "Multi-chip integrated circuit packaging structure" discloses a multi-chip packaging structure using a lead frame. The lead ...

AI Technical Summary

Problems solved by technology

[0002] Multi-chip package (multi-chip package, MCP) is a packaging technology that is getting more and more attention at present. It integrates multiple chips of different or the same type, even including passive components, into a semiconductor package structure to achieve Complete functions or high capacity characteristics, but its electrical conduction path will become more complicated, so the commonly used multi-chip package chip carrier is a multi-layer circuit substrate. In order to reduce packaging costs, some people try to use multi-chip package Replacement of multi-layer circuit substrates with low-cost lead frames

[0003] China Taiwan Patent Publication No. 428875 "Multi-chip Integrated Circuit Packaging Structure" discloses a multi-chip packaging structure using a lead frame. The lead frame includes a chip socket and a plurality of guide pins, and a plurality of chips are attached to the chip. On the socket, use a lead tape (TAB tape) to connect the pads of the chips and the leads to eliminate the difficulty of connecting the bonding wires. However, the current electrical connection machine of the lead frame They are all wire bonding machines. Applying TAB technology on lead frames will involve changes in packaging equipment and wire bonding consumables. In addition, the current lead strips or additional substrates above the chip holder are quite expensive and not practical.

[0004] see figure 1 As shown, the current common multi-chip packaging structure using a lead frame is to arrange a plurality of chips 30, 40, 50 on a chip holder 10 of a lead frame, and a plurality of bonding wires 61, 62, 63, 64 for electrical Connect the chips 30, 40, 50 to the corresponding pins 20 of the lead frame, wherein the bonding wires 61 connect the chip 30 to the nearer pins 20, and the bonding wires 62 connect the chip 40 to the closer The pins 20 on the near side, these bonding wires 63 connect the chip 50 to the pins 20 on the near side. When the chip 50 needs to be electrically connected to the wires 20 on the far side, it must be connected directly by bonding wires. Across the chip 30 or 40, so that the bonding wire is too long and it is easy to punch the wire when pressing the mold, so part of the bonding wire 64 is to connect the chip 50 and the chip 30 first, and the active surface of the chip 30 should be designed with a transfer The circuit is connected to the lead pin on the far side of the chip 50 by other bonding wires 61. Therefore, the chip must have a special conductive circuit or a dummy bonding pad design, and it is impossible to integrate multiple general circuits. Designed semiconductor chips on chip pads on a leadframe

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