Dynamic clock system and method designed for low power

Abstract

The invention discloses a system for generating multiple clock signals in a computer system. The system includes a circuit for generating a core clock signal, a system bus clock signal and a peripheral clock signal. The frequency of one of the clock signals can be lowered or changed without changing the oscillation frequency of the other clock signal. The invention also discloses a method for generating multiple clock signals in a computer system.

Description

technical field [0001] The invention relates to a clock generation method and system for a computer system, in particular to a system and method for generating multiple clocks with multiple oscillation frequencies in a computer system. Background technique [0002] Processors (eg, microprocessors, central processing units, etc.) are widely used in various products and applications, from desktop computers to portable electronic devices, such as mobile phones, laptop computers and personal digital assistants (PDAs). Compared with low-end product processors for their simplified design and inexpensive products and applications, some processors emphasize their powerful performance (for example, processors used in high-end computer workstations). [0003] Usually performance and energy consumption are opposite to each other. Generally speaking, a high-performance processor operates faster or has a more complex design, so it consumes more power than a low-performance processor. A...

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Problems solved by technology

However, as shown in the previous example, if the circuit design of the computer system is configured in series to generate synchronous clocks, since the system bus and peripheral clock signals are derived from the core clock signal, reducing the frequency of the core clock signal will also reduce the system bus with the frequency of the peripheral clock signal

As mentioned above, when the CPU is waiting for peripheral or bus operations to complete, reducing the frequency of the core clock signal according to this scheme will also reduce the frequency of the peripheral and system bus clock signals, while the system bus and / or peripheral bus Already busy, reducing the frequency of its clock signal will result in reduced system performance

[0008] like figure 1 Another disadvantage of reducing power consumption by reducing the frequency of the core clock signal when the system's CPU is idle in the example shown is that the programmable clock dividers used to derive the clock signal typically require one or more Instructions to complete the configuration, in order to reduce the frequency of the core clock signal, such a system must execute one or more instructions to reprogram the frequency divider to reduce the frequency of the clock signal, and then must execute one or more instructions to restore the frequency of the clock signal The standard may be raised again, which is not an ideal proposal

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