Chip packaging structure and method of producing the same

A technology of chip packaging structure and manufacturing method, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problems of adhesive overflow contaminating solder pads and contaminating circuits, etc.
CN100533721CInactive Publication Date: 2009-08-26POWERTECH TECHNOLOGY
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
POWERTECH TECHNOLOGY
Publication Date
2009-08-26
Estimated Expiration
Not applicable · inactive patent

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Abstract

This invention relates to a packaging structure of chips and a manufacturing method including: providing a base board with at least one open-end through it, forming a block element surrounding the open-end of the board, forming an adhering element around the block element, setting a chip on the board and covering the open-end and fixing it with the adhering element on the board, in which, the active surface of the chip is facing to the open-end and part of which exposes it, utilizing a conduction connection element to pass through the open and connect with the active surface of the chip and the bottom surface of the base board electrically and forming a packaging colloid to wrap the element, in which, when the block element is set around the open to resist against adhering the chip, the overflow of the adhering element pollutes the conducting connection points on the active surface of the chip and limits height of the adhering element to reduce the probability of harming the active surface of chips by dust (such as EMC fillers).
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Description

technical field

[0001] The invention relates to a chip packaging structure and a manufacturing method thereof, in particular to a window-opening type chip packaging structure and a manufacturing method thereof for preventing adhesive overflow. Background technique

[0002] With the rapid development of the semiconductor industry, the design of electronic products in IC (integrated) components is developing towards the demand for multi-pin count and multi-function, and the appearance of components is also developing towards the trend of light, thin, short and small. Therefore, the packaging process also faces many challenges, such as the increasingly complex design of the lead frame, the selection of packaging materials, warping of thin packages, heat dissipation and structural strength, etc. These are all problems encountered by the current packaging industry.

[0003] Known general windowed ball grid array package structure, such as Figure 1A As shown, a circuit substrate ...

Claims

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