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Redistribution layer for wafer-level chip scale package and method therefor

A technology of metal layer and dielectric layer, which is applied in the field of forming wafer-level chip size packaging, and can solve the problems of reducing the reliability of packaged IC devices, thinning connection traces, bad etching, etc.

Active Publication Date: 2010-02-03
盛投资有限责任公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This poor etch can create an open connection between the bond pad and the metal trace or a thinned connection trace
This thinning of the traces reduces the reliability of the packaged IC device

Method used

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  • Redistribution layer for wafer-level chip scale package and method therefor
  • Redistribution layer for wafer-level chip scale package and method therefor
  • Redistribution layer for wafer-level chip scale package and method therefor

Examples

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Embodiment Construction

[0024] Although the present invention can be modified into various modifications and alternative forms, the characteristics of the present invention are shown through examples in the drawings, and these characteristics will be described in detail below. However, it should be understood that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0025] It has been found that the present invention is useful in preventing the etching of a thin Ti barrier layer and the underlying Al / NiV / Cu layer (six layers of Al / NiV / Cu / Ti / NiV / Cu metal), and the etching of NiV / Cu on the top layer During the process, the etching will cause an open connection of the metal trace between the bonding pad and the bump pad of the IC device. The photoresist is used to provide an additional barrier l...

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PUM

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Abstract

In an example embodiment, there is a method for packaging an integrated circuit device (IC) having a circuit pattern (305) in a wafer-level chip-scale (WLCS) package (300). The method includes depositing a metal layer (5, 10, 15) on a first dielectric layer (315) and filling (20) in bond pad openings (310) and bump pad openings (330); the metal layer (360) has a top (340) and bottom (360) layer. In the metal layer (360), bond pad connections (310) and bump pad connections (330) are defined (25, 30) by removing the top layer of metal in areas other than at bond pad openings (310) and bump pad openings (330), and leaving the bottom layer (360) of metal in areas without bond pad or bump pad connections. In the bottom metal layer, connection traces between the bond pad and bump pad are defined(35, 40). A second organic dielectric layer (325) is deposited (45) on the silicon substrate (305), enveloping the circuit pattern. The second organic dielectric layer is removed (50) from the bump pad connections exposing the bump pads (330).

Description

Technical field [0001] The present invention relates to integrated circuit (IC) packaging. Specifically, the present invention relates to the formation of a wafer-level chip-scale package that includes a metal that redistributes the bond pads of a peripheral array with a very narrow pitch on an IC device into a bump pad with a larger pitch. Floor. Background technique [0002] The electronics industry is increasingly relying on the development of semiconductor technology to implement higher-functional devices in tighter areas. For many applications that achieve higher functions, devices need to integrate a large number of electronic devices on a single silicon wafer. As the number of electronic devices on a given unit area of ​​a silicon wafer increases, the manufacturing process becomes more difficult. [0003] Semiconductor devices with many different applications in many disciplines have been manufactured. Such silicon-based semiconductor devices usually include metal-oxide-...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60H01L23/485
CPCH01L2924/01015H01L2924/01023H01L24/02H01L2924/13091H01L2924/01029H01L2924/00013H01L2924/01022H01L2224/0401H01L2924/01028H01L24/11H01L2924/01013H01L2924/014H01L2924/30107H01L2924/01024H01L24/13H01L2924/19043H01L2924/14H01L2924/01033H01L2924/01005H01L2924/01006H01L2924/10329H01L2924/01074H01L23/3114H01L2924/01078H01L2924/01014H01L2224/131H01L23/525H01L2924/1306H01L2924/1305H01L2224/02331H01L2224/05008H01L2924/0001H01L24/03H01L24/05H01L2224/05024H01L2224/13024H01L2224/13099H01L2924/00H01L2224/02
Inventor 迈克尔·C·洛
Owner 盛投资有限责任公司