Multi-chip stack encapsulation method

Abstract

A multi-chip stacking and packaging method comprises: a lead frame is composed of a plurality of inner pins and a plurality of external pins, the inner pins comprise a plurality of parallel first inner pin group and a parallel second inner pin group, and center approaching regions of the first inner pin group and the second inner pin group are respectively provided with radiating fins; a first chip is fixedly connected to the lower surface of the lead frame, and the first chip is provided with an active surface and a plurality of first welding pads; a plurality of first metal leads are formedto electrically connect the first welding pads on the first chip, the first inner pin group and the second inner pin group; and a second chip is fixedly connected to the upper surface of the lead frame, and the second chip is provided with an active surface and a plurality of second welding pads.

Description

technical field [0001] The present invention relates to the packaging structure of integrated circuits, in particular to a multi-chip stack packaging method combined with LOC (Lead on Chip) and COL (Chip on Lead) technologies. Background technique [0002] In recent years, three-dimensional (3D) packaging is being carried out in the back-end manufacturing process of semiconductors, in order to use the least area to achieve higher density or memory capacity. In order to achieve this goal, a method of using chip stacked (chip stacked) to achieve three-dimensional (Three Dimension; 3D) packaging has been developed at this stage. [0003] In the known technology, for example, U.S. Patent No. 6,744,121 discloses a structure that uses a lead frame to form a multi-chip stack, such as Figure 1a shown. Obviously, in the package structure shown in Figure 1, in order to prevent the metal wires of the lower chip from contacting the back of the upper stacked chip, the lead frame is ben...

AI Technical Summary

Problems solved by technology

However, the lead frame that has been bent many times is easily deformed, making it difficult to align subsequent chips

In addition, the bent lead frame will make the package structure loose, making it impossible to reduce the package volume

In addition, since the lead frame has been bent many times, the adhesion area between each chip and the lead frame is insufficient, and it is easy to cause the chip to detach during the film injection process.

[0004] In addition, in US Patent No. 6,838,754 and US Patent No. 6,977,427, a structure using a lead frame to form a multi-chip stack is also disclosed, such as Figure 1b and Figure 1c As shown, similarly, in Figure 1b and Figure 1c In all embodiments, it is possible that in the process of bonding the upper chip and the lower chip, the back of the upper chip contacts the metal wire on the lower chip, causing problems such as short circuit or metal wire peeling.

[0005] In addition, when multiple chips are stacked in a package, the multi-chip stack structure will generate thermal effects during operation; if the thermal effect cannot be quickly discharged out of the multi-chip stack structure, the reliability of the chips will be reduced.

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