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Data processing method of high speed multidigit parallel data bus

A technology of data bus and data processing, which is applied in the direction of data exchange network, digital transmission system, time division multiplexing usage, etc. It can solve the problem that multi-bit parallel data bus cannot realize equal-length transmission, and achieve the effect of improving reliability

Inactive Publication Date: 2007-07-18
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a data processing method of a high-speed multi-bit parallel data bus, solve the problem that the multi-bit parallel data bus cannot realize equal-length transmission on the PCB, and then solve the problem of data communication between the data processing units in the broadband system problem, improve the reliability of data transmission

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  • Data processing method of high speed multidigit parallel data bus
  • Data processing method of high speed multidigit parallel data bus

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Embodiment Construction

[0018] The data processing method of high-speed multi-bit parallel data bus of the present invention, comprises the steps:

[0019] The data bus division step divides the data bus into several clock domains, each clock domain transmits a part of the multi-bit parallel data bus, and at the same time ensures that the data lines and clock lines inside each clock domain are transmitted with equal lengths to ensure phase consistency. In this way, the data can be correctly sampled at the receiving end. In the present invention, it is assumed that the bit width of the data bus is M, and it is divided into N groups;

[0020] In the clock division step, at the sending end, the reference clock generates N clocks with the same frequency and phase through the zero-delay clock driver, and divides them into N different clock domains for synchronizing the data in the group;

[0021] The data plane definition step is to define the N different clock domains after the above division as a data p...

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Abstract

This invention discloses a data process method for high speed multi-bit parallel data buses, which divides a multi-bit parallel data bus into multiple clock domain transmissions in the same frequency and phase with the reference clock at the transmission end, the receiving end utilizes the FIFO queue of the read clock and write clock in the same frequency and phase with the reference clock as the buffer storage to recover the multi-bit parallel data bus, the data lines in the clock domains are equal to the clock lines.

Description

technical field [0001] The invention relates to a data communication system, in particular to a method for processing a high-speed multi-bit parallel data bus, which effectively completes the multi-bit parallel data processing with a bus frequency up to hundreds of megahertz. Background technique [0002] Data communication systems are increasingly developing towards high-speed broadband. Communication systems with bandwidths of 10 Gigabit and tens of Gigabit are not uncommon. The 10 Gigabit router or switch at the core of the network is responsible for data processing and exchange, and the network processor performs data packet or cell communication. Classification, routing and traffic management processing, switching network for non-blocking exchange of data, there are several communication methods between the network processor and the switching network, one is a high-speed differential line, but this method requires additional Adding a serial-to-parallel conversion unit r...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/56H04L5/22
Inventor 王志忠刘衡祁陈颖
Owner ZTE CORP