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Centralized scheduling controller for intelligent multi buffer management and dynamic scheduting method

A multi-buffer and centralized scheduling technology, which is applied in the field of microelectronics, can solve the problems of not being able to meet the needs, and achieve the effects of reducing unresponsive time, ensuring bandwidth requirements, and improving throughput and storage resource utilization.

Inactive Publication Date: 2007-08-29
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In the current SOC system, there are generally multiple buffers in the data communication part, and the typical buffer solution can no longer meet the needs of the existing system

Method used

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  • Centralized scheduling controller for intelligent multi buffer management and dynamic scheduting method
  • Centralized scheduling controller for intelligent multi buffer management and dynamic scheduting method
  • Centralized scheduling controller for intelligent multi buffer management and dynamic scheduting method

Examples

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Embodiment Construction

[0034] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figure 3 is a system structure diagram of the intelligent multi-buffer management centralized dispatch controller of the present invention connected with other modules of the system. The connection relationship between the centralized dispatch controller (302) and each module of the system is as follows:

[0036] With the external data receiving and sending unit (301): the external data receiving and sending unit can send a read or write access request to the centralized scheduling controller, and the request of the external data receiving and sending unit can be specified through the endpoint input after being authorized. Buffers accessed;

[0037] With internal data receiving and sending unit (303): The internal data receiving and sending unit can send read or write access requests to the centralized scheduling controller. After the req...

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PUM

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Abstract

Multiple buffer areas are realized by a piece of sharing memory unit in hardware, and managed by unified access arbitrator and allocation table of buffer area in order to provide high performance multiple buffer areas for buffer area access unit. When buffer areas are requested to access, the access arbitrator determines whether there is space allowed to assigning to buffer area requested first based on allocation table; if yes, the access is authorized, and corresponding update is made for the allocation table of buffer area. Buffer area is recovered in real time after its use is ended. The invention raises use ratio of whole memory unit, real time operation and throughput of buffer area.

Description

Technical field [0001] The invention belongs to the field of microelectronics technology, and specifically relates to a centralized scheduling controller for multi-buffer management, and in particular to a dynamic scheduling method for centralized scheduling and performance optimization of intelligent multi-buffer management. Background technique [0002] In traditional data communication systems, there are generally multiple sending and receiving buffers. The sending buffer is used to temporarily store the data to be sent. After the sender finishes sending the last data, it can immediately get the data from the sending buffer and send it without waiting for the data source to provide data. If the sending buffer is empty, then Indicates that there is currently no data to be sent. The receiving buffer temporarily stores the data received by the data receiving device, providing fast storage space, because removing the data often takes longer than the received data. If the received ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/54G06F12/08G06F12/0831H04L12/861
Inventor 周维周晓方孙承绶
Owner FUDAN UNIV
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