Symmetrical multiple processor blade server

A symmetric multi-processor and blade server technology, applied in the field of blade servers, can solve the problems of insufficient number of server CPUs and inability to meet application requirements, and achieve the effects of convenient expansion, low price, and increased computing speed

Active Publication Date: 2007-10-24
DAWNING INFORMATION IND BEIJING +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a symmetrical multi-processor blade server, which can provide 8-way, 16-way or even more than 32-way multi-CPU computing environment, aiming at the defect that the number of CPUs in the existing blade server is insufficient and cannot meet various application requirements. , to meet the user's various large computing needs

Method used

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  • Symmetrical multiple processor blade server
  • Symmetrical multiple processor blade server
  • Symmetrical multiple processor blade server

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0018] An embodiment of the present invention, as shown in Figure 1, includes two computing blades, two CPU chipsets 1 are arranged on each computing blade, a hyper-threading extension unit is arranged on each computing blade, each computing The CPU chipsets on the blades and the CPU chipsets of different computing blades are connected to each other through hyper-thread extension units.

[0019] In this embodiment, the CPU chipset and the hyper-thread extension unit adopt the Intel Xeon product EM64T, and the specified instructions in the blade server memory are extracted by the CPU chipset, and the CPU chipset interacts with other components in the blade server through the hyper-thread extension unit. The CPU chipset communicates and arbitrates, selects the CPU chipset that executes the specified instruction, and transmits the specified instruction to the selected CPU chipset through the hyper-thread extension unit, and the selected CPU chipset executes the specified instructi...

Embodiment 2

[0021] A preferred embodiment of the present invention, as shown in Figure 2, includes two computing blades, and two CPU chipsets are arranged on each computing blade, and the CPU chipset includes a CPU chip, a system request queue, and an intersection latch. Arbitration logic unit, the CPU chip is bidirectionally connected to the system request queue, the arbitration logic unit is bidirectionally connected to the system request queue, and the hyperthread extension unit is bidirectionally connected to the intersection latch arbitration logic unit.

[0022] In this embodiment, the CPU chipset and the hyper-thread extension unit adopt AMD Opteron product AMD64, and the specified instructions in the blade server memory are extracted by the CPU chipset through the memory controller, and the CPU chipset is connected to the blade through the hyper-thread extension unit. Other CPU chipsets in the server communicate and arbitrate, select the CPU chipset that executes the specified inst...

Embodiment 3

[0024] Another preferred embodiment of the present invention, as shown in Figure 2, includes two computing blades, and two CPU chipsets are set on each computing blade, and the CPU chipset includes a CPU chip, a system request queue, an intersection A latch arbitration logic unit, a super transfer unit and a memory controller, the CPU chip is bidirectionally connected to the system request queue, the arbitration logic unit is bidirectionally connected to the system request queue, and the hyperthreading extension unit is bidirectionally connected to the intersection latch arbitration logic unit connected, the super transfer unit and the memory controller are bidirectionally connected to the intersection latch arbitration logic unit respectively.

[0025] In this embodiment, the CPU chipset and hyper-threading expansion unit adopt AMD Opteron product AMD64, as shown in Figure 3, the specified instruction in the blade server memory is extracted by the CPU chip through the memory c...

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Abstract

The invention discloses a symmetry multi-processor blade server, belonging to blade server technical field, for resolving the defects of prior blade server which has inadequate CPU number, to fail to meet applications. The invention can provide a multi-path operation condition with 8 paths, 16 paths or 32 paths, or the like to meet large operation need of user. The invention comprises at least two calculation blades, while each calculation blade is at provided with a CPU chip group, wherein each calculation blade is provided with an ultra-process expander, the CPU chip groups of each operation blade and the CPU chip groups of different calculation blades are connected via the ultra-process expander. The invention more particularly can be used for the application with massive data.

Description

technical field [0001] The invention relates to a blade server, in particular to a symmetrical multi-processor (SymmetricalMulti-Processing) blade server. Background technique [0002] Compared with minicomputers, blade servers must have the characteristics of convenient expansion, strong versatility, and low price, and it is impossible to set too many CPUs on the single-chip computing blades of blade servers. Therefore, the computing blades of existing blade servers mainly use 2 CPU design, only a small number of 4-channel CPU design, but in the application of super-large data processing such as scientific computing, multi-CPU computing equipment with 8-channel, 16-channel or even more than 32-channel can meet the various needs of the application, currently The defect that the number of CPUs in single-chip computing blades is relatively small has restricted the application of blade servers in many fields. Contents of the invention [0003] The purpose of the present inve...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/16G06F15/17
Inventor 曾宇沙超群
Owner DAWNING INFORMATION IND BEIJING
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