Selective precharging circuit for memory device with charging compensating structure

Abstract

The invention discloses a storage device selective pre-charging circuit with a charging compensation structure. The selective pre-charging unit is composed of a pre-charging tube Mp1 and two or more than two bit line selection tube Mpi; the charging compensation unit is composed of a charging compensation tube Mp2 and a second phase inverter inv2; the source end of the pre-charging tube is connected to a power source and its leakage end is connected to an internal circuit; the pre-charging tube Mp1 is controlled by a pre-charging signal Fpre; one end of each bit line selection tube is connected to the bit line in a storage array and its another end is connected to the leakage end of the pre-charging tube Mp1 and the charging compensation tube Mp2, the second phase inverter inv2 of the charging compensation unit as well as the input end of a first phase inverter inv2 in an output drive unit; the source end of the charging compensation tube Mp2 is connected to the power source and its leakage end is connected to the internal circuit; the mp2 tube is controlled by the output end of the second phase inverter inv2; the input end of the second phase inverter inv2 is connected to the leakage end of the pre-charging tube Mp1 and the charging compensation tube Mp2. Therefore, the invention, with simple structure, is able to shorten the time consumed in the bit line charging stage and enhance the reading speed of the storage device.

Description

technical field [0001] The invention mainly relates to the design field of low-power memory, in particular to a memory selective precharging circuit with a charging compensation structure. Background technique [0002] As the density and operating frequency of integrated circuits continue to increase as described by Moore's Law, the design of low-power systems has become the focus of designers. In a microprocessor, especially a SoC (System on a Chip), since the memory occupies a large part of the power consumption of the chip, the design technology of the low-power memory is of great significance to the development of the integrated circuit. With the extensive use of embedded memories in high-performance processors, there are high requirements for the performance of the memory in terms of speed, area and power consumption. However, due to the mutual constraints among these three parameters, memory low-power consumption techniques often cause speed and area overhead. Theref...

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Problems solved by technology

However, it can be seen from the working timing diagram that in order to ensure that the bit line can be precharged correctly, this structure will bring nearly double the overhead of the data reading time (t 2 ≈t 1 ), which is obviously unacceptable for high-speed memory

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