Imaging device
A camera device and electrode technology, applied in radiation control devices and other directions, can solve problems such as difficult data readout, potential fluctuation, and dispersion deviation
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no. 1 approach
[0031] First, the structure of the CMOS image sensor of the first embodiment will be described with reference to FIGS. 1 to 5 . In addition, in the first embodiment, a case where the present invention is applied to a passive type CMOS image sensor as an example of an imaging device will be described.
[0032] The CMOS image sensor of the first embodiment includes, as shown in FIG. 1 , an imaging unit 51 including a plurality of pixels 50 arranged in a matrix, a row selection register 52 , and a column selection register 53 .
[0033] As a cross-sectional structure of a pixel 50 of the CMOS image sensor according to the first embodiment, as shown in FIGS. 2 and 3 , an element isolation region 2 for isolating each pixel 50 is formed on the surface of a p-type silicon substrate 1 . In addition, on the surface of the p-type silicon substrate 1 of each pixel 50 surrounded by the element isolation region 2, the n - The transmission channel 3 composed of type impurity regions, the p...
no. 2 approach
[0064] In this second embodiment, unlike the above-mentioned first embodiment, an example will be described in which an off signal (low level signal), the potential of the transfer channel 3 under the transfer gate electrode 7 and the readout gate electrode 11 is adjusted to be lower than the potential of the transfer channel 3 under the multiplication gate electrode 8, transfer gate electrode 9 and transfer gate electrode 10. Low potential (high barrier).
[0065] Here, in the second embodiment, as shown in FIG. 10 , the clock signals Φ2, Φ3, and Φ4 are supplied to the multiplication gate electrode 8, the transfer gate electrode 9, and the transfer gate electrode 10 through the wiring layers 21, 22, and 23, respectively. In the case of a signal (signal of low level), a voltage of about 0 V is applied to the multiplication gate electrode 8 , the transfer gate electrode 9 and the transfer gate electrode 10 . In addition, at this time, the transfer channel 3 under the multiplic...
no. 3 approach
[0081] In this third embodiment, unlike the above-mentioned second embodiment, an example will be described in which an off signal (low level signal), the potentials of the transfer channel 3 under the transfer gate electrode 7 and the readout gate electrode 11 are respectively different potentials, and are adjusted to be lower than the potentials of the multiplication gate electrode 8, the transfer gate electrode 9 and the transfer gate electrode 10. The potential of the transmission channel 3 is low (high potential barrier).
[0082] Here, in the third embodiment, as shown in FIG. 15 , the clock signals Φ2, Φ3, and Φ4 are supplied to the multiplication gate electrode 8, the transfer gate electrode 9, and the transfer gate electrode 10 via the wiring layers 21, 22, and 23, respectively. In the case of a signal (signal of low level), a voltage of about 0 V is applied to the multiplication gate electrode 8 , the transfer gate electrode 9 and the transfer gate electrode 10 . At...
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