Multi-chip stacking type packaging structure

A technology of packaging structure and stacking structure, which is applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems of unable to stack chips, unable to reduce the thickness of stacked packages, and unable to chip

CN101131992AInactive Publication Date: 2008-02-27CHIPMOS TECH INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Publication Date
2008-02-27
Estimated Expiration
Not applicable · inactive patent

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Abstract

The present invention provides a multi-chip-stacked package, and includes: a substrate set with several metal terminals and a multi-chip-stacked package are provided; the multi-chip-stacked package is fixed on substrate, of which active surface of each chip is set with several welding pads, and each chip is set with insulating layer on its back; a clinging layer combines the active surface of each chip and the insulating layer set on the back of the other chip to form stack structure; several metal wires joins the several welding pads on the several chips and the several metal terminals on the substrate.
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Description

technical field

[0001] The present invention relates to a multi-chip stacking package structure, and in particular to a multi-chip stacking structure in which a reverse lead bonding process and an insulating layer are used to reduce the arc of metal wires, and the adhesive layer of the multi-chip stacking structure is added with Approximate spherical packaging structure. Background technique

[0002] In recent years, three-dimensional (3D) packaging is being carried out in the back-end process of semiconductors, in order to use the least area to achieve relatively large semiconductor integration (Integrated) or memory capacity. In order to achieve this goal, a method of using chip stacked (chip stacked) to achieve three-dimensional space (Three Dimension; 3D) packaging has been developed at this stage.

[0003] In the known technology, the chip stacking method is to stack multiple chips on the substrate, and then use a wire bonding process to connect the multiple chips to t...

Examples

Embodiment Construction

[0061] The direction discussed in the present invention is a way of using multi-chip stacking to stack multiple chips with similar sizes into a three-dimensional packaging structure. In order to provide a thorough understanding of the present invention, detailed packaging structures and packaging steps will be presented in the following description. Obviously, the practice of the present invention is not limited to the specific details of the manner in which chips are stacked that are familiar to those skilled in the art. On the other hand, well-known chip formation methods and detailed steps of back-end processes such as chip thinning are not described in detail to avoid unnecessary limitations of the present invention. However, for the preferred embodiments of the present invention, it will be described in detail as follows, but in addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and the scope of the present ...