Multi-chip stacking type packaging structure

Abstract

The present invention provides a multi-chip-stacked package, and includes: a substrate set with several metal terminals and a multi-chip-stacked package are provided; the multi-chip-stacked package is fixed on substrate, of which active surface of each chip is set with several welding pads, and each chip is set with insulating layer on its back; a clinging layer combines the active surface of each chip and the insulating layer set on the back of the other chip to form stack structure; several metal wires joins the several welding pads on the several chips and the several metal terminals on the substrate.

Description

technical field [0001] The present invention relates to a multi-chip stacking package structure, and in particular to a multi-chip stacking structure in which a reverse lead bonding process and an insulating layer are used to reduce the arc of metal wires, and the adhesive layer of the multi-chip stacking structure is added with Approximate spherical packaging structure. Background technique [0002] In recent years, three-dimensional (3D) packaging is being carried out in the back-end process of semiconductors, in order to use the least area to achieve relatively large semiconductor integration (Integrated) or memory capacity. In order to achieve this goal, a method of using chip stacked (chip stacked) to achieve three-dimensional space (Three Dimension; 3D) packaging has been developed at this stage. [0003] In the known technology, the chip stacking method is to stack multiple chips on the substrate, and then use a wire bonding process to connect the multiple chips to t...

AI Technical Summary

Problems solved by technology

Obviously, this method of stacking packages with spacers 130 cannot reduce the thickness of the stacked packages, so the number of chips that can be stacked is limited.

[0006] In the stacked package structure in Fig. 1 and Fig. 2, there is also a common problem, that is, the setting position of the spacer 130 cannot give full support to the upper chip (120b; 20), so when performing wire bonding (wire bonding) , if the chip is too thin, it may cause the chip to be broken during the wire bonding process (wafer broken)

Therefore, the chips in the stacked package structure using the spacer 130 need to have a certain thickness, so this stacked package structure cannot stack too many chips.

In addition, in the process of chip stacking, there may also be a problem that the upper chip (120b; 20) contacts the lower wire 140, resulting in a short circuit

In addition, in the stack package structure with the spacer 130, after the wire bonding process is completed, the molding is performed, but since the distance between the upper and lower chips is only the thickness of the spacer 130 or the spacer layer 50 , so it may form a void in the gap between the upper and lower chips. When the bubble is expanded by high temperature, it will cause cracks in the encapsulant

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