Method for realizing bare nucleus software debugging in multicore processor
A technology for multi-core processors and debugging tasks, applied in the field of communications, can solve problems such as inability to debug multi-core processors, and achieve the effects of facilitating development and debugging, shortening solution time, and enhancing competitiveness
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Embodiment 1
[0034] When the multi-core processor is limited by the allocation of IP addresses, the software debugging solution shown in Figure 3 can be used. Correspondingly, the debugging single board of the multi-core processor adopts the structural setting shown in Figure 1 . With this implementation method, the control plane core is required to act as a proxy, and the debugging request information is distributed to the data plane core for the second time. The control plane core 103 in FIG. 3 acts as a proxy. After the distributor extracts the destination IP address, it judges that the IP address is identical to the IP address of the data plane core (105, 106), then through the proxy of the control plane core 103, the distributor distributes the debugging notification information to the data plane core (105) for the second time. , 106). If after the distributor extracts the destination IP address, it judges that the IP address is the same as the IP address of the control plane core 104...
Embodiment 2
[0054]When the multi-core processor is not limited by the number of IP addresses, the software debugging scheme shown in FIG. 4 can be used. Correspondingly, the debugging single board of the multi-core processor adopts the structural setting shown in FIG. 2 . With this implementation method, the control plane core is not required to act as a proxy. After the distributor extracts the destination IP address, it can determine that the IP address is consistent with one or more IP addresses in the control plane core (103, 104) or data plane core (105, 106). If they are the same, the distributor directly sends debugging notification information to the control plane cores (103, 104) or data plane cores (105, 106).
[0055] The second embodiment is described in detail below, the method for realizing bare-core software debugging in the multi-core processor of the present invention, please refer to accompanying drawing 4, and its implementation process includes the following steps:
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