39results about How to "Easy to develop and debug" patented technology

This invention provides a method for protecting information safety inside chips based on the JTAG port control, in which, said chip includes: a non-volatile medium used in storing JTAG lock on instruction, a JTAG locking controller used in controlling the border scan chain of the JTAG port and its registor, and the method includes: when the chip is turned on, the JTAG locking controller detects the JTAG lock-on instruction and judging if the instruction has be written into the JTAG instruction storage unit, the controller cuts off the border scan chain to stop the work of the port registor and controls a program guide of the chip to let it refuse leading codes from outside to inside.

The invention discloses a virtual serial port screen simulation system and a simulation method thereof. The virtual serial port screen simulation system comprises a resource reading module, a display driving module, a touch screen driver, a serial port communication module, a command processing module, a storage module and a main program module, wherein the resource reading module provides an interface for reading an image resource, a font library resource and a system configuration resource, the display driving module provides a display-related interface, and the touch screen driver realizes touch compression action detection and reads touch coordinate parameters; the serial port communication module provides an interface for receiving and transmitting data by virtue of a serial port and records communication historical data; the storage module is used for storing system parameters and a control state of a serial port screen; and the main program module builds the modules into a complete and executable program. The virtual serial port screen simulation system has the advantages that a developer can directly complete development and debugging of the serial port screen on a PC, the resource is avoided from being repeatedly downloaded to the serial port screen for many times, and time of the developer is saved.

The invention provides a control system for a robot. The system comprises an operation center module, a control module and a data bus which are mounted in one circuit board, wherein the operation center module comprises a plurality of parallel operation modules used for parallel operation, and a real-time operation module used for real-time operation; the control module is used for controlling one or more data acquisition modules used for acquiring posture and position information of the robot, controlling one or more driving modules used for adjusting the motion direction and speed of the robot, and controlling one or more power management modules used for supplying power to the robot; and the data bus is connected with the modules included in the system and is connected with external network. Compared with the prior art, the control system has the advantages that the plurality of modules are integrated, and the plurality of parallel operation modules are adopted to increase the operation speed, so that the control system for the robot is highly integrated, and a robot control kernal hardware system is small is size, light in weight and convenient to mount, develop and debug.

The invention discloses a microcontroller real-time data transmission device and a microcontroller real-time data transmission method. The device comprises three parts including a debugging target, a protocol converter and a debugging host, wherein the debugging target comprises a target microcontroller for operating debugged program and is provided with an SPI (serial peripheral interface), in addition, the SPI is provided with a DMA (direct memory access) channel, the protocol converter comprises a relay microcontroller, the relay microcontroller is provided with an SPI and an Ethernet communication module, and the debugging host is a computer and is provided with an Ethernet card. The method comprises the following steps that the real-time data of program variables required in a memory of the debugging target is sent to the protocol converter by the SPI through the DMA channel, the protocol converter carries out protocol conversion on the received data, in addition, the data is transmitted to the debugging host through UDP/IP (user datagram protocol/Internet protocol) via the Ethernet, and the data is displayed to users after being processed by the debugging host and is stored into files.

The invention relates to a communication chip architecture based on an IEC 61158 standard field bus, which comprises an internal data bus control unit, a DMA field bus data transmission unit and a configuration unit; wherein, the internal data bus control unit is controlled by the configuration unit to finish the data transmission from the CPU data bus to the DMA field bus data transmission unit through the cache of the internal RAM memory; the DMA field bus data transmission unit is controlled by the configuration unit to finish the data transmission from the internal RAM memory of the internal data bus control unit to the field bus, and also to finish the data receiving and the data transmission of identifying information from the field bus to the internal RAM memory of the internal data bus control unit; and the configuration unit is controlled by an external CPU to finish the data transmission from the configuration information of the field bus data transmission to the internal data bus control unit and the DMA field bus data transmission unit. The invention is in accordance to the IEC 61158 specifications, facilitates development and debugging and also improves the work efficiency of microcontrollers.

The invention relates to the field of development of circuit boards and discloses a voltage reduction conversion circuit achieving adjustable voltage. According to the voltage reduction conversion circuit achieving adjustable voltage, by adjusting an adjustable resistor RX1 of a resistor-adjustable unit, the output voltage of a voltage reduction conversion chip is changed, and therefore stable output of different target voltages can be achieved, the voltage reduction conversion circuit achieving the adjustable voltage has higher practicability, development and debugging of a circuit board are facilitated, fine adjustment of output voltage can also be achieved, and it is avoided that the chip works under an overvoltage state or an undervoltage state.

The invention discloses an SQL-based API interface system, which comprises an interface development module, an interface management module, an interface authentication module and an interface monitoring module, and is characterized in that the output end of the interface development module is connected with the input end of the interface management module, and the output end of the interface management module is connected with the input end of the interface authentication module; the output end of the interface authentication module is connected with the input end of the interface monitoring module, and the output end of the interface monitoring module is connected with the input end of the interface management module; the management method comprises the steps of interface development, interface management, interface authentication and interface monitoring. The method has the advantages that various existing data sources are supported, the application scene is expanded, the interface safety is high, and the whole life cycle of the interface is managed.

The invention discloses a PG (program guidance) signal control method and device. The method includes the steps: acquiring all PG signals on a single plate; performing corresponding delay for the PG signals serving as enable signals, and outputting the processed PG signals; storing parameters of the all PG signals; acquiring instructions of a serial port acquiring the PG signals, and outputting corresponding PG signals. The device comprises an acquiring component, a first output component, a storage component and a second output component, the acquiring component is used for acquiring the all PG signals on the single plate, the first output component is used for performing corresponding delay for the PG signals serving as the enable signals and outputting the PG signals, the storage component is used for storing the parameters of the all PG signals, and the second output component is used for acquiring the instructions of the serial port acquiring the PG signals and outputting the corresponding PG signals. According to the method and the device, the all PG signals on the single plate can be uniformly managed and stored in a module, and later development and later debugging are facilitated.

The method is as the follows: character string information used for device identification is fetched from information bank stored with circuit board drawing and treatment is carried out to attribute of character string to satisfy ruled identification direction and character style, an identification regional series (IRS) formed by multiple subregion of candidate identification (CI) is confirmed around device according to distance value of appointed device identification to corresponding device and a CI subregion suitable to place device identification is confirmed from the IRS according to avoidane of priority control as well as device identification is generated at the identification subregion.

The invention discloses a processor chip simulator. A simulation chip is provided with a nonvolatile memory controller and a nonvolatile memory, a power supply detection module receives and detects the power supply signal of outside for the processor chip through a power supply signal line, the power supply detection module is connected with the simulation chip through a simulation chip reset signal line, and is connected with the nonvolatile memory controller through a nonvolatile memory reset signal line; if the processor chip stops supplying power, an effect reset signal is output to the nonvolatile memory controller by the power supply detection module; and if the power supply detection module detects that the processor chip supplies power again, the effective reset signal is output tothe simulation chip. The invention also discloses a power failure test method for the processor chip simulator. By use of the processor chip simulator and the power failure test method, the power failure characteristics of the nonvolatile memory can be simulated.

The invention relates to a data storage device and method based on a SAFEBus and belongs to the technical field of 659 buses. The storage and the export of 659 bus data are realized by adopting a datastorage module. The method is characterized in that a processor reads, encrypts and stores the 659 bus data in a built-in electronic disk: in a running mode, and the processor records the 659 bus data to the built-in electronic disk. In a maintenance mode, a serial port and a network port are externally arranged by utilizing the built-in electronic disk, and the data in the built-in electronic disk is read. The data storage module saves the 659 bus data in a period of time, debugging personnel can retrieve the 659 bus data at a certain particular moment (such as a failure point moment) duringthe period to enhance the maintainability of the 659 bus data. Through encrypting and storing the 659 bus data, the data security is guaranteed; through adding a timestamp, the data conversion is simultaneously performed on the 659 bus data, so that the 659 bus data at a certain particular moment is conveniently found by adopting retrieval software. The data storage device and method provided bythe invention have the benefit that the 659 bus is convenient to debug, so that the product research and development efficiency is improved.

The invention discloses a hardware control system for a block cipher algorithm. The system comprises a key expansion module, a process scheduling module, an input data caching module, a round key/configuration information caching module, an encryption and decryption processing module, an output management module and an output data caching module, wherein the encryption and decryption processing module comprises N groups of encryption/decryption modules for performing cryptographic operation, and each group of encryption/decryption modules comprises a round operation module and x round encryption/decryption operation units. According to the hardware control system of the block cipher algorithm, key expansion and parallel processing of n independent encryption/decryption operations are realized through flow scheduling, and the operation speed is improved; full parallel or local parallel operation of block cipher algorithm round operation is completed through a round operation scheduling module in the encryption/decryption module, and configuration of the number of the encryption/decryption modules and the number of round operation units is achieved, so better solutions of resources and speeds are achieved under data streams of different speeds.

The invention discloses a wireless debugging system for an embedded development board. The wireless debugging system comprises a DAPLINK debugging module, a first wireless communication module and a second wireless communication module; the DAPLINK debugging module is connected with an SWD interface of an embedded development board and is used for acquiring log data from the embedded development board or writing debugging data; the first wireless communication module is connected with the DAPLINK debugging module and is used for wirelessly transmitting and receiving data of the DAPLINK debugging module; the first wireless communication module is in wireless connection with the second wireless communication module; and the second wireless communication module is connected with a computer. According to the wireless debugging system and method for the embedded development board, the wireless communication module is connected through the DAPLINK debugging module, so that development debugging, log extraction and program updating of equipment are more convenient and simpler, and the development efficiency and the iteration efficiency are effectively improved.

The invention discloses an HTML5 package installation test method and device, computer equipment and a storage medium. The method comprises the steps of obtaining an MEID number of an HTML5 package sent by a mobile terminal and an installation path of the HTML5 package; detecting whether the computer terminal has an update code for the HTML5 packet or not; and when an update code is detected, transmitting the update code to the corresponding MEID mobile terminal through the installation path, and refreshing and displaying a result according to the update code. The method is mainly applied to adevelopment test process; the updated HTML5 program code does not need to be sent to the mobile terminal for verification after being compressed and packaged; the HTML5 packet is directly transmittedto the mobile terminal from the computer terminal and stored in the path stored in the HTML5 packet in the mobile terminal, the mobile terminal refreshes the display page, and then the display page is immediately displayed according to the newly updated code, so that the development and debugging process is more convenient, and the test is quicker.