Hardware control system of block cipher algorithm

A block cipher algorithm, hardware control technology, applied in transmission systems, digital transmission systems, electrical components, etc., can solve the problems of increasing project time and cost, long hardware algorithm debugging cycle, etc., to achieve easy development and debugging, easy to adapt to adjustment, The effect of shortening the development cycle

Active Publication Date: 2022-01-14
湖南麒麟信安科技股份有限公司
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  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the long period of modification and debugging of the hardware algorithm, it is easy to increase the project time cost when the application is frequently switched

Method used

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  • Hardware control system of block cipher algorithm
  • Hardware control system of block cipher algorithm
  • Hardware control system of block cipher algorithm

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Embodiment Construction

[0054] It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0055] In the following description, use of suffixes such as 'module', 'part' or 'unit' for denoting elements is only for facilitating description of the present invention and has no specific meaning by itself. Therefore, 'module', 'part' or 'unit' may be used in combination.

[0056] see Figure 1-18 , in order to achieve the above object, a hardware control system for implementing block cipher algorithm is provided in the first embodiment of the present invention, including: key expansion module KE, process scheduling module PC, input data cache module BFI, round key / configuration Information cache module BFC, n groups of encryption / decryption modules MMn (where n is a positive integer), output management module OC, and output data cache module BFO.

[0057] The key expansion module KE includes the key data input ...

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Abstract

The invention discloses a hardware control system for a block cipher algorithm. The system comprises a key expansion module, a process scheduling module, an input data caching module, a round key/configuration information caching module, an encryption and decryption processing module, an output management module and an output data caching module, wherein the encryption and decryption processing module comprises N groups of encryption/decryption modules for performing cryptographic operation, and each group of encryption/decryption modules comprises a round operation module and x round encryption/decryption operation units. According to the hardware control system of the block cipher algorithm, key expansion and parallel processing of n independent encryption/decryption operations are realized through flow scheduling, and the operation speed is improved; full parallel or local parallel operation of block cipher algorithm round operation is completed through a round operation scheduling module in the encryption/decryption module, and configuration of the number of the encryption/decryption modules and the number of round operation units is achieved, so better solutions of resources and speeds are achieved under data streams of different speeds.

Description

technical field [0001] The invention relates to the technical field of computer security, in particular to a hardware control system of a block cipher algorithm. Background technique [0002] The block cipher algorithm is a method of encrypting plaintext by performing multiple row shifts, column confusion, finite field operations, and byte substitutions on the data segments after dividing the plaintext into data segments of a specific length. It has the advantages of fast encryption speed, easy to implement safe and reliable encryption of large amounts of data, easy to standardize design, and parallel computing, so it has been widely researched and applied in the field of information security. Common block cipher algorithms mainly include: SM4 algorithm, DES algorithm, 3DES algorithm, AES algorithm, IDES algorithm, etc. [0003] There are two main implementations of the block cipher algorithm: software implementation and hardware implementation. The software implementation...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L9/06
CPCH04L9/0618H04L2209/122
Inventor 刘魁汪鹊平彭勇申锟铠刘文清杨涛
Owner 湖南麒麟信安科技股份有限公司
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