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Method for protecting chip internal information security based on JTAG port control

A technology for internal information and port control, applied in computer security devices, internal/peripheral computer component protection, instruments, etc., can solve problems such as non-compliance, long cycle, difficult embedded software development, etc., to facilitate online upgrades, guarantee safe effect

Active Publication Date: 2007-08-22
HANGZHOU SYNOCHIP DATA SECURITY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] 1. Lost boundary scan function;
[0007] 2. Due to non-compliance with IEEE1149.1 specification, the support of third-party tools is lost;
[0008] 3. Unable to simulate and debug in real time, the development of embedded software is difficult and the cycle is long;
[0009] 4. Cannot effectively block the attack of off-chip software;
The disadvantage of this method is that the fusing process is irreversible, once the fusing, the chip can no longer recover
This method is suitable for simple and cheap microcontrollers, but not for complex and expensive high-end processors or SOCs
[0011] In the prior art, there is no information security protection method that allows the chip to enjoy the convenience brought by the JTAG interface and has sufficient security.

Method used

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  • Method for protecting chip internal information security based on JTAG port control
  • Method for protecting chip internal information security based on JTAG port control
  • Method for protecting chip internal information security based on JTAG port control

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Embodiment Construction

[0039] The present invention will be further described below in conjunction with the accompanying drawings.

[0040] The specific realization and the effect of realization of the present invention will be described below by taking the PS1803DSP safety microcontroller chip as an example.

[0041] PS1803 is a DSP microcontroller designed on the basis of ZSP400 core. It integrates 128K bytes of embedded FLASH, 156K bytes of RAM, and also integrates USB port, UART, SPI, I2C port, and NAND FLASH interface , can be attached to fingerprint sensor, NANDFLASH and other peripheral devices at the same time. As long as the firmware is written into the on-chip FLASH, a dedicated SOC can be constructed.

[0042] The entire set of software of the fingerprint electronic signature device is very complicated, including not only encryption and decryption algorithms, but also image processing and fingerprint recognition algorithms, as well as the simulation and control of U disk. Fingerprint el...

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PUM

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Abstract

This invention provides a method for protecting information safety inside chips based on the JTAG port control, in which, said chip includes: a non-volatile medium used in storing JTAG lock on instruction, a JTAG locking controller used in controlling the border scan chain of the JTAG port and its registor, and the method includes: when the chip is turned on, the JTAG locking controller detects the JTAG lock-on instruction and judging if the instruction has be written into the JTAG instruction storage unit, the controller cuts off the border scan chain to stop the work of the port registor and controls a program guide of the chip to let it refuse leading codes from outside to inside.

Description

technical field [0001] The invention belongs to the technical field of a system chip (SOC), and in particular relates to a method for protecting chip internal information security based on JTAG port control. Background technique [0002] With the improvement of the design level of large-scale integrated circuits, it is the general trend to integrate a variety of ICs with different processes into a single chip to build a SOC (system on chip), and SOC-based products are becoming more and more popular in the market. SOC can make the whole machine product composed of discrete IC devices lower in cost, lower in power consumption, and higher in reliability. [0003] JTAG (Joint Test Action Group, Joint Test Action Group) is an international standard test protocol (IEEE 1149.1 compatible), mainly used for chip internal testing (Boundary Scan [0004] However, with the improvement of chip integration, the contradiction between openness and security is becoming more and more promine...

Claims

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Application Information

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IPC IPC(8): G06F21/00G06F21/76
Inventor 邱柏云裴育
Owner HANGZHOU SYNOCHIP DATA SECURITY TECH CO LTD
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