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Embedded DRAM with increased capacitance and method of manufacturing same

A capacitor and electrode technology, applied in the field of embedded dynamic random access memory, can solve the problems of increasing the cost and complexity of the manufacturing process

Inactive Publication Date: 2008-03-12
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0018] However, this method requires a large number of masking steps, increasing the cost and complexity of the fabrication process

Method used

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  • Embedded DRAM with increased capacitance and method of manufacturing same
  • Embedded DRAM with increased capacitance and method of manufacturing same

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Experimental program
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Embodiment Construction

[0031] 2, a DRAM device including a cylindrical cell capacitor according to an exemplary embodiment of the present invention includes a semiconductor substrate 10 having an active region including a source or drain 20 covered by an electrode 21. The extension of the active region is covered by the spacer 24 surrounding the gate 22 covered by the gate electrode 23. An insulating layer 30 is also provided on the electrodes 21 and 23 and the separator 24, and a first insulating layer 27 (for example, a pre-metalized dielectric, hereinafter referred to as PMD1 layer) is provided on the insulating layer 30. The PMD1 layer 27 is patterned using photolithography and etching to form node contact holes or trenches that pass through the insulating layer 30 to expose the active region, and the trenches are filled with conductive material to form contacts Column 25.

[0032]Next, an end stop layer (ESL) 40 is deposited on the contact pillar 25 and the PMD1 layer. Then, a first portion of the ...

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PUM

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Abstract

An embedded DRAM memory device comprising one or more cylinder type cell capacitors. Contact pillars (25) are provided in a PMD layer (27) on a substrate (10), and the lower (or storage mode) electrodes of the capacitors are formed by depositing an end stop layer (40) over the contact pillars (25) and then forming second contact trenches (62) in an oxide layer (60) provided over the PMD layer (27). The second contact trenches (62) are aligned with respective contact pillars (25) and filled with, for example, a barrier material plus tungsten. The oxide layer (60) is selectively etched at the location of the contact trench (62) to the end stop layer (40). The end stop layer etched and the PMD layer (27) is subsequently etched along a portion of the length of the first contact pillar (25) to form a trench (62). Finally, the tungsten in the second contact trench (62) is selectively etched through the barrier layer, so as to leave a barrier layer (64) e.g of TiN, on the inner walls and floor of the second trench (62).

Description

Technical field [0001] The present invention relates to an embedded dynamic random access memory (DRAM) with increased capacitance, and more particularly to a method of forming a high-performance capacitor for use in such a device. Background technique [0002] There are currently several trends in semiconductor manufacturing and electronic processes, which are dedicated to continuous minimization of device size and power consumption. One reason for this trend is to make more portable devices that are relatively small and easily portable, and therefore tend to rely on relatively small batteries as their main power source. For example, cellular phones, personal computing devices, and personal sound systems are some of those devices that are increasing in demand in the consumer market. In addition to the continuous decrease in size and the increase in portability, personal devices are required to have more and more computing power and on-chip memory. In accordance with these requir...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8242H10B12/00
CPCH01L27/10852H01L27/10855H01L28/91H01L28/90H01L27/10817H10B12/318H10B12/0335H10B12/033
Inventor 韦罗妮克·德容厄奥德丽·贝尔特洛特
Owner NXP BV