[0038] Referring to Figure 1, the graphics OSD controller integrated in the video processing chip of the present invention has an internal basic structure including a bitmap data decompression module, a storage operation control module, a programmable color mapping module, an OSD image scaling module, and an OSD image display management Module, register operation management module and MCU interface module; the user sets each register and control parameter output of the register operation control module through the MCU interface, thereby completing various functions such as storage operation, color mapping and display synthesis.
[0039] After bitmap data is compressed, it can effectively reduce the storage space requirements for off-chip bitmap data. The bitmap data decompression module is used to decompress OSD data into bitmap index data. The data compression uses an improved run-length coding (BLE) algorithm, and the compression part is implemented by software.
[0040] The storage operation control module uses off-chip SDRAM memory and on-chip dual-port RAM resources to realize the functions of writing, storing, generating and displaying OSD image data.
[0041] The programmable color mapping module uses the color mapping table (OSD_LUT) stored on the chip to map the input original image index data stream into a 24-bit pseudo-color data stream in RGB space, and realize the mapping and conversion of image index values to color space.
[0042] The OSD image scaling module uses the bilinear image interpolation method to flexibly adjust the size of the generated OSD image in both horizontal and vertical directions to adapt to different formats of video signals or different resolution display terminals.
[0043] The OSD image display management module can control the overlay mode of multi-layer graphics OSD data, the mixing mode of the OSD image and the original video signal, the size of the OSD image display window, and the display characteristics according to the parameter settings of the OSD controller.
[0044]The register operation management module can be operated by the user to set various parameters of other modules, and control various modes such as the writing of OSD original image materials, storage control and display characteristics.
[0045] The MCU interface module provides serial and parallel working modes, which are used to set various display parameters and operating parameters of the register operation management module, so as to control the storage and display of OSD data and read the status of the OSD controller.
[0046] Under the control of the register operation management module, the decompressed OSD index data flows through the storage operation control module to control the writing into the OSD data storage area, and complete the transport from the data storage area to the display buffer area under the control of the module. When the image is displayed, the storage operation control module reads out the index data of the OSD display buffer area, and is converted into a 24-bit image data stream in RGB space by the programmable color mapping module. The image data can flexibly adjust the resolution of the image through the OSD image scaling module, and finally superimpose with the original video signal under the control of the effective signal (OSD_ACTIVE) generated by the OSD image display management module.
[0047] As shown in Figure 2, the storage resources used in the design of the present invention include off-chip SDRAM memory and on-chip dual-port RAM memory. The off-chip SDRAM memory is divided into an OSD data storage area and an OSD display buffer area; the off-chip SDRAM memory and on-chip dual-port RAM resources are controlled by the storage operation control module to realize the functions of writing, storing, generating and displaying OSD image data.
[0048] The off-chip SDRAM memory is generally used as a frame memory by the video processing chip, and the present invention shares the space of the SDRAM to store OSD graphic menu data. The shared SDRAM space is divided into two parts, the OSD data storage area and the OSD display buffer area. Among them, the OSD data storage area stores the bitmap material of the OSD graphic design, and the OSD display buffer area stores the OSD graphic interface to be displayed. The input buffer (INPUT_BUFFER), the output buffer (OUTPUT_BUFFER), and the accelerated buffer (VAC_BUFFER) are all dual-port memories, which can read and write to the SDRAM with the cooperation of the storage control module. OSD_LUT is an address mapping table composed of a 256x24bits dual-port RAM, which maps 8-bit image index data to 24-bit data in RGB space. SCALE_BUFFER is a storage array composed of 2048x24bits dual-port RAM, which provides row storage for the OSD image scaling module.
[0049] It can be seen that the key of the present invention lies in the design of the storage operation control module, which needs to be able to flexibly perform read and write operations on the SDRAM, and maximize the utilization of the bus bandwidth for integration. The structure block diagram of the storage operation control module designed by the present invention is shown in FIG. 3.
[0050] The arbitration module arbitrates the read and write requests and display acceleration request signals, and generates corresponding control signals to complete multi-task scheduling.
[0051] The write request module generates a write request signal by detecting the stack depth of the input buffer (INPUT_BUFFER). Similarly, the read request module and the display acceleration request module respectively generate read requests and read requests by detecting the stack depth of the output buffer (OUTPUT_BUFFER) and acceleration buffer (VAC_BUFFER). Speed up the read and write request signal. The arbitrator (Arbitrator) arbitrates read and write requests and display acceleration request signals, generates corresponding allow signals, and stimulates the address generation and command generation module to generate SDRAM address signals and read and write control commands. The design of the storage control unit fully considers how to improve bandwidth utilization, and combined with the characteristics of SDRAM, the following three technologies are mainly adopted:
[0052] (1) Using the Burst access mode of SDRAM, the data can be read and written continuously in multiple bytes;
[0053] (2) Use the address mapping method to read and write the same row unit of SDRAM as much as possible to reduce the row address generation in the read and write operations;
[0054] (3) Utilize the multi-bank structure of SDRAM to hide the operation cycle required for row operation and precharge.
[0055] The storage operation control module includes an arbiter, an address generation module, a command generation module, an input buffer module, an output buffer module, and an accelerated buffer module. The address generation module, the command generation module are connected with the arbiter, and the input buffer module is connected to the arbiter through a write request Connected, the output cache module is connected to the arbiter through a read request, and the acceleration cache module is connected to the arbiter through an acceleration request.
[0056] OSD display acceleration technology is integrated in the storage operation control module design. The design of the current OSD menu is becoming more and more complex, and a large amount of bitmap data needs to be read and written during interface switching, which easily causes a delay in the screen display. Display acceleration technology can copy the bitmap data stored in the OSD data storage area without intermediate intervention to the OSD display buffer area, and can complete the copy, move and block of the OSD data block in the display buffer area (DisplayBuffer) Operations such as filling can improve the response time of the OSD menu, effectively save OSD storage resources, and improve OSD programming efficiency.
[0057] The state diagram of OSD storage task scheduling is shown in Figure 4. If the "write request" WR_REQ is valid, the bus control is given to "write"; if the "read request" RD_REQ is valid, the bus control is given to "read"; if the "acceleration request" VAC_REQ is valid, the bus control is given to "acceleration" . If the two request signals are valid at the same time, the arbiter Arbitrator arbitrates according to the respective stack depth information and ensures that no data omission occurs in each operation.
[0058] When the OSD controller is integrated with the video processing chip, the SDRAM control module in the chip can be used, and task scheduling for OSD reading and writing and display acceleration can be added.
[0059] The OSD image scaling module can use the bilinear interpolation (Bilinear) method to scale the same OSD graphic material in both horizontal and vertical directions to support different video formats and display terminals with multiple resolutions. Bilinear interpolation is a linear calculation method that calculates the pixel value of the point to be interpolated based on the surrounding 4 image points. Taking the calculation of one-dimensional space as an example, Figure 5 is a schematic diagram of the relationship between the pixels of the bilinear interpolation. The original image point is represented by A[i,j], and the point to be interpolated is represented by B[i,j]. The pixel value of the point to be interpolated is calculated by the following formula:
[0060] B[i,j]=(1-d)*A[i,j]+d*A[i+1,j]
[0061] The functional block diagram of the OSD image scaling module is shown in Figure 6. The module is composed of six units: data storage, control signal generation, write control, read control, mapping parameter calculation, and interpolation calculation. The image is scaled using bilinear interpolation, and the size of the generated OSD image is flexibly adjusted in both horizontal and vertical directions to adapt to video signals of different formats or display terminals of different resolutions. OSD image scaling module includes data storage, interpolation calculation module, write control module, read control module, control signal generation module, mapping parameter calculation module; the control signal generation module is separately associated with the write control module, read control module, and mapping parameter The calculation module is connected, the writing control module and the reading control module are connected with the data storage, the data storage is connected with the interpolation calculation module, and the mapping parameter calculation module is connected with the reading control module and the interpolation calculation module respectively.
[0062] The module generates a write control signal by the control signal generating unit to control the write module to generate the address of the write data memory. OSD image data is written into the data memory buffer under the control of the write signal and address. The mapping parameter calculation module calculates and generates the readout index i and the distance parameter d according to the control signal and the scaling factor. The read control unit generates a read address according to the control signal and the index parameter i, and reads the pixel values A[i, j] and A[i+1, j] of the interpolation reference point from the data memory. The interpolation calculation unit calculates the pixel value of the interpolation point according to the pixel value of the interpolation reference point and the distance parameter d. The OSD image scaling module can support 1/2 to 2 times scaling of the original OSD image in 1/64 steps to support different display terminals.
[0063] The OSD controller can support the composite display of up to 4 OSD layers. Before color mapping, the decompressed data of each layer is represented by an 8-bit bitmap index. The principle of OSD image synthesis is shown in Figure 7. Under the control of the layer selection signal and the background color register, the various layers of the OSD are superimposed in a shielding manner, and the superimposed 8-bit OSD bitmap index is color-mapped and converted into 24-bit RGB pixel data. In addition, the OSD window detection module generates the OSD effective area flag signal OSD_ACTIVE according to the position parameters of the OSD (including the starting point coordinates of the window OSD_SX, OSD_SY and the horizontal and vertical sizes of the window OSD_WX, OSD_WY, etc.), and is used to control the OSD and video data Overlay. OSD transparency setting signal OSD_TRANS is used to control the superposition ratio of OSD and video signal to achieve various transparency effects such as 1/2 and 1/4.
[0064] The OSD controller has two MCU operation interfaces, serial I2C and parallel, which is more flexible to the register operation mode inside the controller:
[0065] (1) When using a parallel interface, the OSD internal register file is accessed as the external data storage space of the MCU. Therefore, only a simple MOVX instruction is required to achieve the control purpose.
[0066] (2) The I2C interface logic only needs two signal lines: SDA (data line) and SCL (serial clock line). The I2C serial communication protocol in the interface processing module is implemented by a synchronous state machine. The state transition diagram is shown in Figure 8, including start signal detection, receiving master address, response, receiving slave address, receiving data, output data, operation Stop waiting for 12 states. After reset, the module is in the start signal detection state. When SCL is high, the falling edge of the data line SDA from high to low is regarded as the start signal. After the start signal is detected, I2C will start receiving data once. (Transfer) process. According to the characteristics of I2C read and write operations, some states of read and write are shared in the design to make rational use of resources. In addition, an anti-interference circuit is added to the controller to ensure stable I2C operation.
