Insulated-gate semiconductor device

Abstract

The present invention relates to insulated-gate semiconductor device. Setting p<+> type impurity area below a gate pad electrode, the end portion of the p<+> type impurity area has sphere-shaped curvature. When the reverse breakdown voltage between drain-source electrodes reaches hundreds volts, an electric field at the sphere-shaped end portion will collect so that it can not obtain adequate drain-source reverse breakdown voltage. In a plane field, when augmenting the curvature of the angle portion of the p<+> type impurity area, it will lose the quantity of transistor unit configured in motion area. A channeling area connecting with the transistor unit is also configured below the gate pad electrode, and is fixed as source electric potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in polysilicon with a stripe shape below the gate pad electrode.

Description

technical field [0001] The present invention relates to an insulated gate type semiconductor device, and more particularly to an insulated gate type semiconductor device capable of sufficiently securing an operating region area and maintaining a high reverse withstand voltage. Background technique [0002] In a conventional insulated gate semiconductor device, a transistor cell is not disposed under a gate pad electrode (for example, refer to Patent Document 1). [0003] In addition, a plurality of protective diodes such as pn junctions may be connected in series under the gate pad electrode. In addition, in some cases, a diffusion region of high-concentration impurities is formed on the substrate below the gate pad electrode in order to ensure the reverse withstand voltage between the drain and the source. [0004] Figure 11 (A), (B) as a conventional insulated gate semiconductor device shows that a P + An example of an n-channel MOSFET with an impurity region. [0005] ...

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Problems solved by technology

Therefore, in the graphs of FIG. 12(A) and (B), part of the transistor cells near the gate pad electrode 48 cannot be arranged, and p + Type impurity region 49 control (design change) and the need to reduce the operating region (transistor cell layout area)

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