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Iterative test generation and diagnostic method based on modeled and unmodeled faults

A modeling and error technology, applied in the direction of error detection/correction, electronic circuit testing, digital circuit testing, etc., can solve the problems that conventional technology is not enough to effectively deal with test problems, test time cannot be managed, etc., to improve tester time , Improve the effect of error resolution ability

Inactive Publication Date: 2008-04-30
IBM CORP
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AI Technical Summary

Problems solved by technology

Given the ever-increasing circuit density in chips, which is a major contributor to IC speed and performance, test times quickly become unmanageable
The complication of this problem is that conventional techniques are insufficient to handle testing problems effectively

Method used

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  • Iterative test generation and diagnostic method based on modeled and unmodeled faults
  • Iterative test generation and diagnostic method based on modeled and unmodeled faults
  • Iterative test generation and diagnostic method based on modeled and unmodeled faults

Examples

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Embodiment Construction

[0038] In the following, a preferred embodiment of the invention is described, showing several system components that are closely and interactively linked to the test pattern generation and tester execution process.

[0039] Referring to Figures 2-5, the flow and functional components of the iterative diagnosis process are shown. Test generation, error simulation, and diagnostic simulation blocks have inputs from logic design and error models. The test generation block provides a production test mode and a custom repeat diagnostic mode, labeled N-detection mode in the corresponding figure. Other specialized algorithms are also invoked to generate custom patterns, which are described below.

[0040] The diagnostic and test execution process is repeated calling the adaptive fault device specific iterative process multiple times until the desired diagnostic resolution is achieved.

[0041] The process steps preferably include:

[0042] 1. Use standard diagnostic techniques to ...

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Abstract

The present invention relates to a method for repeated test generation and diagnosis based on modeled and unmodeled errors. In particular, it relates to diagnostic and characterization tools applicable to structural VLSI design to address issues associated with error tester interaction pattern generation and methods to efficiently reduce diagnostic testing time while achieving higher fault resolution capabilities. Empirical fault data drives the creation of adaptive test patterns that localize faults to precise locations. This process is repeated until the necessary positioning is achieved. Both fault signatures and associated annotations, as well as fault signatures and adaptive patterns, are stored into a library to facilitate diagnostic resolution. Parallel tester applications and adaptive test generation provide efficient use of resources while reducing overall test and diagnostic time.

Description

technical field [0001] The present invention relates to the field of design automation for very large scale integration (VLSI) circuits, and more particularly to methods for testing and subsequently diagnosing faults against a wide range of modeled and unmodeled errors. Background technique [0002] Frequently encountered problems when testing and subsequently diagnosing VLSI devices is the availability of efficient test patterns and precise diagnostic methods that pinpoint the root causes of a wide range of modeled and unmodeled errors. The rapid integrated development of VLSI devices and their associated high circuit performance and complex semiconductor processes has exacerbated both previous and introduced new types of defects. This defect diversity, together with a limited number of erroneous models, often results in large and inappropriate collections of patterns with ineffective diagnostic resolution. [0003] Identifying errors in large logical structures and pinpoi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28G01R31/317
CPCG01R31/318364G01R31/318342G06F11/261
Inventor F·莫提卡P·T·德兰M·P·库斯科T·J·弗莱斯曼
Owner IBM CORP
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