Packaging structure for maintaining pin supporting plane on mould sealing wafer

Abstract

The invention relates to an encapsulation structure kept on the pin supporting plane of a mould encapsulating wafer, which consists essentially of a plurality of pins of an LOC conductor frame, wafers pasted under the pins, a plurality of wire solders electrically connected with the wafers and the pins, a plurality of first props arranged over part of the pins, a plurality of second props arranged under part of the pins and an encapsulating colloid. The encapsulating colloid is the internal ends to encapsulate the wafer, the wire solders and the pins; also the encapsulating colloid is the side walls of the first and second props; wherein, the first props and the second props are longitudinally corresponding and near the wafer. Besides, the total thickness of the corresponding first and second props and the corresponding pins equals approximately to the thickness of the encapsulating colloid. The props can avoid wafer excursion during encapsulation and prevent water back and wire solder from exposing.

Description

technical field [0001] The present invention relates to a lead-on-chip (LOC) semiconductor packaging structure, in particular to a packaging structure that maintains the lead-on-chip support plane during molding. Background technique [0002] In a low-cost semiconductor package structure, a Lead-On-Chip (LOC, hereinafter referred to as LOC) type lead frame is used as a chip carrier, such as a thin small outline package (Thin Small Outline Package). Package, TSOP). The so-called LOC lead frame refers to the design of the lead frame without a die pad. The chip is directly pasted under the pins of the lead frame. The pins will be skewed during sealing, causing the defect of chip displacement, and in more serious cases, there will be problems of improper bare die and bond wire exposure. [0003] see figure 1 As shown in FIG. 2 , it is a schematic cross-sectional view of a conventional semiconductor package structure of lead-on-chip (LOC). The existing conventional semiconduc...

AI Technical Summary

Problems solved by technology

[0006] The main purpose of the present invention is to overcome the defects in the existing semiconductor packaging structure, and provide a new type of packaging structure that maintains the support plane of the pins on the chip when molding. The technical problem to be solved is to make it The pillars can avoid the problem of chip offset and chip or bonding wire exposed outside the sealant during molding, so it is more suitable for practical use

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