A logic unit for oppositional differential power consumption analysis

A technology of differential power analysis and logic unit, which is applied in the direction of instruments, electrical digital data processing, computer security devices, etc., to achieve the effect of avoiding glitches

Active Publication Date: 2008-05-28
BEIJING TONGFANG MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, not all internal nodes are masked by applying MDPL, and its ANTI DPA capability still needs to be tested in practice

Method used

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  • A logic unit for oppositional differential power consumption analysis
  • A logic unit for oppositional differential power consumption analysis
  • A logic unit for oppositional differential power consumption analysis

Examples

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Embodiment Construction

[0015] see figure 1 , the logic unit of the present invention is connected with the input data and the load through the input and output ports. There are two power balance modules in the logic unit, and the inputs of the power balance modules are four original data respectively. The power consumption balance module one 1.1 output is 01 and the random signal sel is connected to the input of the AND gate one 2.1, and the power consumption balance module one 1.1 output is another road 01n and the random signal sel is connected to the input of the AND gate two 2.2. The output of power consumption balance module 2 1.2 is 01 and the random signal nsel is connected to the input of AND gate 3 2.3, and the output of power consumption balance module 2 1.2 is 01n and the random signal nsel is connected to the input of AND gate 4 2.4. The outputs of AND gate 1 2.1 and AND gate 4 2.4 are connected to the output port OUT of the logic unit through OR gate 1 3.1, and the outputs of AND gate ...

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Abstract

A logic unit confronting differential power analysis relates to the technical field of IC card safety and special device encryption. One output end with 01 output of a first power balance module of the invention and a random signal sel are connected to the input end of a first AND gate, and the other output end with 01n output of the first power balance module and the random signal sel are connected to the input end of a second AND gate; one output end with 01 output of a second power balance module and a random signal nsel are connected to the input end of a third AND gate, and the other output end with 01n output of the second power balance module and the random signal nsel are connected to the input end of a fourth AND gate. The output ends of the first and the fourth AND gates are connected to one outport OUT of the logic unit via a first OR gate, and the output ends of the second and the third AND gate are connected to the other output port OUTN of the logic unit. The two power balance modules and the four AND gates have constant power consumption, and the output ports of the logic unit has statistically balanced power consumption. Compared with the prior art, the invention realizes the power balance of the unit interior and the output and effectively avoids burrs.

Description

technical field [0001] The invention relates to the technical field of IC card security or special-purpose device encryption, in particular to a logic unit against differential power analysis of smart IC cards or special-purpose devices. Background technique [0002] Smart IC cards are used more and more widely, and security issues are becoming increasingly prominent. Among many attack methods, the power analysis method is a very threatening one. Power analysis includes simple power analysis SPA and differential power analysis DPA, and the threat of DPA is particularly great. DPA exploits the correlation between power consumption and input data, and adopts statistical methods to obtain secret information. In the prior art, measures against DPA include random order execution and information hiding INFORMATION BLINDING in terms of software; on the GATE LEVEL level, the common dual-rail pre-charge logic style [DURAL RAIL PRE_CHARGE LOGIC STYLE (DRP)] and hidden logic style [...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/00G06F21/76G06F21/77
Inventor 黄金煌盛敬刚丁义民徐磊霍俊杰侯书珺孟庆云
Owner BEIJING TONGFANG MICROELECTRONICS
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