High-performance ECC coprocessor system resistant to power consumption attack

A co-processor, high-performance technology, applied in the architecture with a single central processor, electrical digital data processing, instruments, etc., can solve the problems of anti-power attack, power attack, long pipeline delay, etc. Area consumption, modularization of rules, easy modularization effect

Pending Publication Date: 2022-03-25
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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  • Application Information

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Problems solved by technology

[0003] The invention provides a high-performance ECC coprocessor system resistant to power consumption attacks, which can solve the problems of long pipeline delay and power consumption attacks

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  • High-performance ECC coprocessor system resistant to power consumption attack
  • High-performance ECC coprocessor system resistant to power consumption attack
  • High-performance ECC coprocessor system resistant to power consumption attack

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Embodiment Construction

[0028] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0029] Such as Figure 1 to Figure 2 As shown, the present invention discloses a high-performance ECC coprocessor system resistant to power consumption attacks, including an ECC main controller, a finite field operation unit, a scalar multiplication module, a random number generator, a hash operation module, a register set and AXI bus interface unit. The function can be realized by mounting the designed coprocessor on the existing RSIC-V-based S...

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Abstract

The invention discloses a high-performance ECC coprocessor system resistant to power consumption attack. The system comprises an ECC master controller, a finite field arithmetic unit, a scalar multiplication module, a random number generator and a hash operation module. The ECC master controller controls all the modules to cooperatively complete operation and feeds back state signals to the register set, basic modular operation is completed by calling the finite field operation unit, then data is sent to the scalar multiplication module, and the functions of the point doubling point operation module, secret key scanning, coordinate conversion, y coordinate recovery and power consumption balance are completed. Wherein the random number generator is used for generating random Z coordinates in scalar multiplication operation, and the Hash operation module completes preprocessing of input messages, so that the efficiency of digital signature is improved, and finally encryption and decryption functions and digital signature verification functions are completed. The method has the advantages of being low in space complexity, simple, regular and easy to modularize, has the advantages of performance and area overhead, and meets the application requirements of ECC in the specific field.

Description

technical field [0001] The invention belongs to the technical field of cryptographic circuit design, and in particular relates to a high-performance ECC coprocessor system resistant to power consumption attacks. Background technique [0002] In recent years, with the rapid development of information technologies such as artificial intelligence, 5G and quantum communication, information security is facing severe challenges. Asymmetric encryption algorithms mainly include DSA, RSA, ECC, IBC, and ELGamal, etc., and ECC is more secure than RSA of the same level, and the key size is smaller. Compared with others, the encryption speed is faster, saving energy, bandwidth and storage. It is widely used as an algorithm with higher security strength, and at the same time, it puts forward higher requirements for the processing speed of the elliptic curve cryptosystem. ECC implementation is mainly divided into hardware implementation and software implementation. Now 5G has become a h...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78G06F21/60G06F21/62
CPCG06F15/7889G06F21/602G06F21/62Y02D10/00
Inventor 张本俊吴宁葛芬周芳费才献
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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