MOSFET with vertical laminated leakage pole structure and its making method
A drain, layered technology, used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as limiting the service life of transistors, and achieve the effects of improving reliability, reducing vertical electric fields, and reducing electric fields.
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[0024] As shown in Figure 2, the present invention provides a MOSFET with a vertical layered drain structure, comprising a semiconductor substrate with a P well, a gate formed on an insulating film on the surface of the P well, and a gate formed on an insulating film on the surface of the P well. a source structure in the surface of the P well, a drain structure formed in the surface of the P well, and a substrate structure formed in the surface of the P well;
[0025] The source structure includes a highly doped N-type diffusion region n+ and an N-type slowly changing diffusion region, and the N-type diffusion region n+ is formed inside the N-type slowly changing diffusion region;
[0026] The substrate structure is a highly doped P-type diffusion region p+;
[0027] The drain structure is a layered sandwich structure perpendicular to the channel, including a highly doped N-type diffused region n+, an N-type slowly changing drain NGRD (N-type graded drain), and a low-doped P...
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