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MOSFET with vertical laminated leakage pole structure and its making method

A drain, layered technology, used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as limiting the service life of transistors, and achieve the effects of improving reliability, reducing vertical electric fields, and reducing electric fields.

Inactive Publication Date: 2008-05-28
GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In high-voltage devices, the vertical and lateral electric fields in the channel increase sharply, so there is a serious reliability problem of hot carrier effect (HCI), which limits the service life of the transistor

Method used

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  • MOSFET with vertical laminated leakage pole structure and its making method
  • MOSFET with vertical laminated leakage pole structure and its making method

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specific Embodiment approach

[0024] As shown in Figure 2, the present invention provides a MOSFET with a vertical layered drain structure, comprising a semiconductor substrate with a P well, a gate formed on an insulating film on the surface of the P well, and a gate formed on an insulating film on the surface of the P well. a source structure in the surface of the P well, a drain structure formed in the surface of the P well, and a substrate structure formed in the surface of the P well;

[0025] The source structure includes a highly doped N-type diffusion region n+ and an N-type slowly changing diffusion region, and the N-type diffusion region n+ is formed inside the N-type slowly changing diffusion region;

[0026] The substrate structure is a highly doped P-type diffusion region p+;

[0027] The drain structure is a layered sandwich structure perpendicular to the channel, including a highly doped N-type diffused region n+, an N-type slowly changing drain NGRD (N-type graded drain), and a low-doped P...

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Abstract

The invention relates to a MOSFET with a vertical layed drain structure, and the drain structure is a layered sandwich structure perpendicular to a channel, and comprises a heavy doped N-type diffusion region n+, a N-type graded drain electrode NGRD, a low doped p-type diffusion region p- and a p-well region, and the heavy doped N-type diffusion region n+, the N-type graded drain electrode NGRD, the low doped p-type diffusion region p- and the p-well region are orderly arranged. When the layed drain electrode structure is fabricated, the light doped diffusion region p- is injected, then the N-type graded drain electrode and the heavy doped diffusion region n+ are injected. The invention provides the MOSFET with the vertical layed drain structure and the preparation method of the drain structure. The invention adopts the layed drain structure perpendicular to the surface direction of the channel to reduce avalanche breakdown effects between the drain electrodes and the substrate below the channel, and the reliability of components can be improved.

Description

technical field [0001] The invention relates to a MOSFET with a vertical layered drain structure and a method for manufacturing the drain. Background technique [0002] High-voltage MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) devices (working voltage higher than 10V) are widely used as drivers in small power products such as LCDs. In high-voltage devices, the vertical and lateral electric fields in the channel increase sharply, so there is a serious reliability problem of hot carrier effect (HCI), which limits the service life of the transistor. Substrate current (I SUB ) is a commonly used and convenient method to characterize HCI. In common transistors, I SUB -I GS The curve has only one I SUB peak, corresponding to the impact ionization of the channel surface. As shown in Figure 1, the substrate current of a high-voltage device has two peaks, the first peak (V GS = 4V, V DS =18V), the second peak (V GS =18V, V DS =18V), at I SUB The first peak co...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/417H01L21/28H01L21/336
Inventor 戴明志叶景良廖宽仰
Owner GRACE SEMICON MFG CORP