Testable integrated circuit, system in package and test instruction set

Abstract

An integrated circuit die comprises a plurality of interconnects including a first test data input (142), a second test data input (144) and a test data output (152), and a test arrangement (100) for testing the integrated circuit die. The test arrangement (100) comprises a further multiplexer (150) coupled to the test data output (152), a multiplexer (140) coupled to the first test data input (142) and the second test data input (144), a plurality of shift registers (102, 104, 106, 108) including an instruction register (108), each of the shift registers being coupled between the multiplexer(140) and the further multiplexer (150) and a controller (110) for controlling the multiplexer (140) and the further multiplexer (150) in response to the instruction register (108). Such a test arrangement facilitates JTAG compliant testing of a system in package (SiP) by providing a direct connection between the SiP test data input pin and the second test data input (144) of the IC die, and the SiP test data output pin and the test data output (152) of the IC die, thus facilitating the bypassing of other test arrangements in the SiP.

Description

technical field [0001] The invention relates to an integrated circuit die comprising a test arrangement. [0002] The invention also relates to a system-in-package comprising an integrated circuit die as described above. [0003] The invention also relates to a set of instructions for manipulating the test configuration. Background technique [0004] Integrated circuit (IC) testing has become an essential part of the IC manufacturing process. In addition, increasing IC complexity makes the test portion of the process cost-dominated. This is one of the reasons for the rise of globally applicable (i.e., standardized) IC test methodologies, as these facilitate the addition of standard test configurations to ICs, thereby reducing test costs. [0005] A common example of such a standardized testing method is the IEEE 1149.1 standard, also known as Boundary Scan Testing (BST) or Joint Test Access Group (JTAG) testing. According to BST, the IC is expanded using a test access po...

AI Technical Summary

Problems solved by technology

While this configuration is JTAG compliant, it is not ideal for SiP testing

First, an additional TAP is required, which increases the area overhead of the SiP

In addition, the interconnection structure between the system-level TAP and the IC-level TAP is relatively complex, which increases the probability of interconnection errors between them

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