Dynamic binary translation method for cooperation design of software and hardware

Abstract

The invention relates to a dynamic binary translating method of software-hardware co-design for realizing a virtual machine coprocessor of a processor chip on a hardware level, which comprises a binary translator unit, a TCache manager unit and the like, wherein management and check of the TCache is realized via the hardware, and fast check of the Tcache is realized in from of instructions, further, as the binary translator unit is realized via the hardware, a master processor executing the object instruction avoids necessary switching to translate, and the start time and the Miss time can be relieved well. The software portion comprises load of heterogeneous executable program, execution of the object instruction, optimization of hot codes and the like. Through tightly coupling of hardware and software, coexistence between the overall virtual machine and the original system can be effectively controlled, thereby achieving internal parallelism. Because single processor supports a plurality of instruction sets, instruction compatibility problem of heterogeneous processors is solved, further, compared with the conventional virtual machine with pure software, properties and transparency are increased, and the speed of the virtual machine can be close to the local execution speed.

Description

technical field [0001] The invention relates to a dynamic binary translation method of software and hardware co-design, which is used to enable a single processor to support multiple instruction sets and solve the instruction compatibility problem of heterogeneous processors. The invention belongs to the technical field of process level virtual machine and binary translation. Background technique [0002] The popularity of a new processor is inseparable from the support of corresponding software. For current processors, compatibility is mainly guaranteed through the instruction set (ISA) interface layer between hardware and software. However, this approach leads to inefficiencies in hardware-software interactions. From a hardware standpoint, processor designers are forced to adapt to the most widely used ISA, regardless of its inefficiencies. Otherwise, there is a risk of being rejected by the market due to software compatibility issues; from a software point of view, sof...

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Problems solved by technology

Intel and AMD's hardware-supported virtualization technologies are aimed at Vmware and Xen's system-level virtual machines, while Transmeta's Crusoe, IBM's Daisy, and Professor James E.Smith's research is to use software and hardware co-designed virtual machines for new For processor design, Kenneth B.Kent aimed at high-level language-oriented virtual machines, which were not suitable for general-purpose processor instruction sets. Gaurav Mittal directly synthesized binary codes to generate underlying hardware, which was expensive to synthesize and generated without with dynamic characteristics

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