Device and method for holding sampling

A sample-and-hold, sample-and-hold technology, applied in instruments, static memory, analog-to-digital converters, etc., can solve the problems of high cost and difficulty of operational amplifiers, and achieve the effects of low magnification, improved reliability, and high gain

Inactive Publication Date: 2009-04-22
北京安策恒兴投资有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In general, in order to achieve these design goals, the desi

Method used

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  • Device and method for holding sampling
  • Device and method for holding sampling

Examples

Experimental program
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Embodiment 1

[0036] Please refer to figure 2, the entire sample-and-hold device is divided into two parts: the first-stage sample-and-hold circuit and the second-stage sample-and-hold circuit. The first-stage sampling and holding circuit and the second-stage sampling and holding circuit are controlled by the timing control circuit, so that the sampling phase of the first-stage sampling and holding circuit corresponds to the holding phase of the second-stage sampling and holding circuit, and the first-stage sampling and holding circuit The holding phase corresponds to the sampling phase of the second-stage sampling and holding circuit, so that the two work together. When the first-stage sample-and-hold circuit is in the sampling phase, its positive and negative output terminals are short-circuited (does not affect sampling), and the second-stage sample-and-hold circuit enters the hold phase at the same time. When the first-stage sample-and-hold circuit is in the hold phase, the second-sta...

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PUM

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Abstract

The invention discloses a sample-and-hold amplifier which comprises a primary sample-and-hold circuit and a secondary sample-and-hold circuit. The input positive terminal and the input negative terminal of the primary sample-and-hold circuit receive an external signal, the output positive terminal and the output negative terminal of the primary sample-and-hold circuit are coupled to the input positive terminal and the input negative terminal of the secondary sample-and-hold circuit, the primary sample-and-hold circuit is provided with a primary operational amplifier with the amplification being less than a multiple, and the secondary sample-and-hold circuit is provided with a secondary operational amplifier which realizes the amplification more than the multiple; after the external signal is sampled, held and amplified, by the primary sample-and-hold circuit and the secondary sample-and-hold circuit, the external signal is output from the output positive terminal and the output negative terminal of the secondary sample-and-hold circuit. Meanwhile, the invention discloses a sample-and-hold method. The sample-and-hold amplifier, as a basic signal processing module, is used for front end processing of the external input signal; and the sample-and-hold amplifier ensures the speed and the precision of the signal conversion with the simple structure on the premise of realizing high reliability.

Description

【Technical field】 [0001] The invention relates to analog and digital signal processing, in particular to a sample-and-hold device and a sample-and-hold method. 【Background technique】 [0002] A sample-and-hold circuit (sample-and-hold) is also called a sample-and-hold amplifier. When the analog / digital conversion is performed on the analog signal, a certain conversion time is required. During this conversion time, the analog signal should remain basically unchanged, so as to ensure the conversion accuracy. The sample and hold circuit is the circuit that realizes this function. [0003] Figure 1a Shown is a traditional sampling and holding circuit, in which the capacitor Cs is both a sampling capacitor and a holding capacitor. When in the sampling phase (sampling time), the switch controls the input and output of the operational amplifier to short-circuit, and the two inputs are also short-circuited at the same time, the switch connected to the external signal is turned on...

Claims

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Application Information

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IPC IPC(8): G11C27/02H03M1/12
Inventor 阮建李崇仁
Owner 北京安策恒兴投资有限公司
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