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Electronic circuit that comprises a memory matrix and method of reading for bitline noise compensation

A technology of memory, memory unit, applied in the direction of static memory, digital memory information, information storage, etc.

Inactive Publication Date: 2009-04-22
NXP BV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this method is only partially effective because complex filters are required to ensure that the correlated response on the bit line is not transferred to the reference line, or the coupling can only be used part of the time when no correlated response occurs.

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  • Electronic circuit that comprises a memory matrix and method of reading for bitline noise compensation
  • Electronic circuit that comprises a memory matrix and method of reading for bitline noise compensation
  • Electronic circuit that comprises a memory matrix and method of reading for bitline noise compensation

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Embodiment Construction

[0014] figure 1 A circuit is shown having a memory matrix 10 comprising a plurality of columns 100 of memory cells. For each column 100 , the circuit includes a respective bit line 12 , differential sense amplifier 14 and reference circuit 15 . For each column 100 , the bit line 12 of the column 100 is the conductor coupled to the memory cells in the column 100 . For each column 100 , the differential sense amplifier 14 for the column 100 has a first input coupled to the bit line 12 of the column 100 and a second input coupled to the output of the reference circuit 15 for the column 100 . For each column 100, the input of the reference circuit 15 for the column 100 is coupled to the bit line 12 for the adjacent column 100 (or the column if the column is at the edge of the matrix).

[0015] Figure 1a One of the reference circuits 15 including a core reference circuit 16 (which is not dependent on a signal on a bit line) and a resistive element 18 coupling the output of the ...

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Abstract

Data are read from a memory matrix (10) with a plurality of bit lines (12). A differential sense amplifier (14) receives a signal derived from a first one of the bit lines (12) on a first input. The differential sense amplifier (14) receives a reference signal from a reference output of a reference circuit (15) to a second input. A second one of the bit lines (12), which is adjacent to the first one of the bit lines (12), is coupled to the reference circuit (15), so that a bit line signal value on the second one of the bit lines (12) affects a reference signal value on the reference output, at least partly reproducing an effect of crosstalk of the bit line signal value (12) on the second one of the bit lines (12) on a bit line signal value on the first one of the bit lines (12).

Description

technical field [0001] The invention relates to a circuit comprising a memory matrix. technical background [0002] As the distance between bitlines decreases, crosstalk between signals on adjacent bitlines of a memory matrix is ​​an increasing problem. US Patent No. 6,639,846 describes a method to solve this problem that includes grounding the bit lines on either side of the bit lines that sense data. Therefore, crosstalk from other bit lines is shielded. However, this reduces the number of bit lines that can be read in parallel. Furthermore, complete shielding is not possible. [0003] Another approach is mentioned in an article titled "Single Event Mirroring and DRAM Sense Amplifier Designs for Improved Single-Event Upset Performance" by Kush Gulati, Lioyd W. Massengil, and Ghasi R. Agrawal, December 1994. Pages 2026-2034 of IEEE Transactions on Nuclear Science Vol 41. This article describes a technique that uses a differential sense amplifier having an input coupled...

Claims

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Application Information

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IPC IPC(8): G11C7/14G11C7/02
CPCG11C7/18G11C7/02G11C7/062G11C7/14
Inventor 维克托·M·G·范艾科特尼古拉斯·兰伯特
Owner NXP BV
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