System, interface card and method for remote upgrading field programmable gate array

Abstract

The present invention discloses a system of remote upgrade field programmable gate array (FPGA), a interface card and a method thereof. The system comprises a mainboard and a interface card, wherein, the interface card comprises the FPGA, a flash memory and the CPLD. The mainboard is used for transmitting the upgrade data sent by a remote network management to the FPGA and transmitting an upgrade starting instruction to the FPGA after receiving the upgrade instructions sent by the remote network management; The FPGA writes the upgrade data transmitted by the mainboard in the flash memory, receives the upgrade starting instruction transmitted by the mainboard and outputs starting signals to the CPLD; according to the time sequence of control signals input by the CPLD, upgrade data in the flash memory is red out to complete configuration; The CPLD receives starting signals transmitted by the FPGA, and outputs a group of time sequences of control signals to the FPGA. Design cost of the interface card is reduced by using the present invention.

Description

technical field [0001] The invention relates to the technical field of remote upgrading, in particular to a system, an interface card and a method for remotely upgrading field programmable gate arrays. Background technique [0002] In order to flexibly respond to the various needs of users in various industries, a large number of communication devices such as routers have applied modular design. The same main board can realize a variety of different interface accesses by configuring different interface cards, providing more users in many industries. For rich, convenient and flexible networking methods, it saves users' investment and reduces the difficulty of users' network maintenance. Among the currently applied interface cards, a large number of bus methods are used in the back end as the Peripheral Component Interconnect (PCI) interface and the Local bus (Local bus) interface, and the high-speed PCI (PCIE) bus may be used in the future. [0003] Since there are many type...

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Problems solved by technology

[0009] 3. There are two master devices, CPLD and FPGA, on the interface card, and a PCI bridge must be added as a bus arbitration

[0010] 4. The CPLD on the interface card and the PCI core of the FPGA must be designed with the same frequency

However, due to the limitation of the CPLD process, it is difficult to implement a 66MHz PCI core on the CPLD. Therefore, when the FPGA works at 66MHz, it is necessary to add a PCI bridge between the FPGA and the CPLD for bus isolation.

[0011] In general, the CPLD required by this solution is large in scale and complex in design, and PCI bridges need to be added, resulting in high overall design costs

In addition, the insertion of the PCI bridge will also reduce the communication efficiency between the FPGA and the motherboard.

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