Virtual FPGA structural modeling and mapping method thereof

Abstract

The invention provides a modeling of an evolvable virtual FPGA structural model based on n input LUTs and a mapping method thereof. The modeling takes arbitrary n input LUTs as basic units of circuit evolution, and a virtual FPGA array structure is formed by the basic units; various virtual FPGA structural models of 2-5 input LUTs are analyzed and compared to obtain an optimal virtual FPGA structural model based on the 3 input LUT; meanwhile, the method maps the virtual structure into an actual FPGA underlying structure, thus realizing the direct operation on the configuration bit string of the FPGA underlying structure. Compared with the prior art, the virtual FPGA structural model set up by the invention can be utilized to improve the evolution efficiency and the utilization rate of FPGA logical resource. Furthermore, the invention has good flexibility and universality.

Description

technical field [0001] The invention relates to a modeling and a mapping method of an evolveable virtual FPGA structure model based on an n-input LUT (look up table), belonging to the field of field programmable gate array (FPGA) electronic design automation technology. Background technique [0002] Evolvable hardware EHW (Evolvable Hardware) [1] is a hardware circuit that can autonomously and dynamically change its own structure and behavior when interacting with the external environment. Therefore, it has a wide range of application prospects in intelligent communication networks, intelligent perception, pattern recognition and artificial intelligence [2]. [0003] The FPGA-based evolvable hardware generally uses the genetic algorithm, a search algorithm, to operate and process the chromosomes composed of the configuration codes of the FPGA, and finally obtain a hardware circuit that can complete the target function on the FPGA. Among the mainstream FPGA-based evolvable h...

AI Technical Summary

Problems solved by technology

This two-layer circuit model is separated from the underlying structure of the FPGA. The common problems are low utilization of logic resources, low evolution efficiency and slow speed. In addition, since these models are strongly dependent on specific applications or evolution goals, that is to say Different applications or evolutionary goals need to build different FPGA models, so the reusability rate is also low and the versatility is poor

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