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Fast divider with 127 multiplied with 2n as divisor

A fast and powerful technology, applied in instruments, electrical digital data processing, digital data processing components, etc., can solve the problems of many components, slow operation speed, complex structure, etc., to achieve low cost, simple structure, and fewer components. Effect

Inactive Publication Date: 2009-08-05
TIANJING UNIV OF TECH & EDUCATION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention aims to solve the problems of complex structure, many components, and slow operation speed in the existing divider technology, thereby providing a divisor whose divisor is 127×2 n , a fast divider when n is 0 or any positive integer

Method used

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  • Fast divider with 127 multiplied with 2n as divisor
  • Fast divider with 127 multiplied with 2n as divisor
  • Fast divider with 127 multiplied with 2n as divisor

Examples

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Embodiment 1

[0019] A dividend is 0~8191×2 n +2 n -1, the divisor is 127×2 n , a divider with fast operation when n=0. Its circuit schematic diagram is as figure 1shown. The connection relationship of the circuit is: I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, and I13 are the input terminals of the divider, which constitute the binary dividend I1I2I3I4I5I6I7I8I9I10I11I12I13; The Y6 pin, Y5 pin, Y4 pin, Y3 pin, Y2 pin, Y1 pin, X7 pin, X6 pin, X5 pin, X4 pin, X3 pin, X2 pin, X1 pin, I1, I2, I3, I4, I5 and I6 are simultaneously connected to the X6 pin, X5 pin, X4 pin, X3 pin, X2 pin, and X1 pin of the addition ADD617, and are also connected to the input pin 1 of the exclusive OR gate XR1, XR2, XR3, XR4, XR5, and XR6. I7 is connected to the input pin 1 of the AND gate A1, and I8, I9, I10, I11, I12, and I13 are simultaneously connected to the input pins 2 of the exclusive OR gates XR1, XR2, XR3, XR4, XR5, and XR6; the exclusive OR gates XR1, XR2, The output pins 3 of XR3, XR4, XR5,...

Embodiment 2

[0026] The dividend is 0~16383, and the divisor is 127×2 n , when n=1, the circuit schematic diagram of the fast operation divider is as follows figure 2 shown. The connection relationship of the circuit is in figure 1 A connection line I141-O141 from input to output is added on the basis of . When the ADD7618 uses a seven-digit binary number plus a seven-digit binary number plus a one-bit binary number, and the sum is an eight-bit binary adder, all positions other than the lowest six bits of the second addend are 0. Other circuit connections are the same as in Embodiment 1.

[0027] When I1I2I3I4I5I6I7I8I9I10I11I12I13I141=(11000000000010)B=(12290)D, because X7, X6, X5, X4, X3, X2, X1 of ADD7618 constitute the first addend of ADD7618, Y6, Y5, Y4, Y3, Y2 of ADD7618 , Y1 forms the second addend of ADD7618, the first addend of ADD7618 is (0000001)B like this, the second addend is (110000)B, (0000001)B+(110000)B=(00110001)B, Get F8 of ADD7618 to be 0, so just constitute the ...

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Abstract

This invention refers to a quick divider having a divider of 127*2n, specifically a special divider composed of connecting different dividers and gates or non-gates. An input end thereof constitutes a dividend of binary system. One output end constitutes a quotient of binary system of division result as well as the other output end constitutes a remainder of binary system of division result. This divider can executes a quick operation while the divider is 127*2n, the dividend is 0 to 8191*2n+2n(-1) and n is equal to the integers of 0, 1, 2, ... 4. The divider with simple structure, less used elements and low cost cannot be replaced in some certain occasions and can be widely applied to the digital signal processing system.

Description

technical field [0001] The present invention relates to the divider in the electronic device, especially a kind of divisor is 127 * 2 n Fast divider when n is 0, 1, 2, 3...n integers. Background technique [0002] Among the various operations of digital signal processing, division is the most complex operation with the most potential to be tapped. In general-purpose CPUs and DSPs, a divider is often not specifically implemented with hardware, because the proportion of division in general applications is very small, and the design of the divider is much more complicated than other computing components, so the usual practice It is to write software on the basis of other computing components such as ALU and / or multiplier to form a division subroutine. However, in specific application fields such as number system conversion and data unpacking, the situation is different. If the division operation occupies a considerable proportion, simply using software for division operation ...

Claims

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Application Information

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IPC IPC(8): G06F7/535
Inventor 刘新钰武金木任健宗燕燕杜洪伟杨旭谷兆麟赵海霞张倩张德林杨娟素董艳艳王伟
Owner TIANJING UNIV OF TECH & EDUCATION
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