Encapsulation structure and method for semi-conductor

Abstract

The invention relates to a ball grid array packaging structure and a packaging method thereof. The packaging structure comprises a circuit board provided with an upper surface and a lower surface. The method comprises the following steps that: firstly, the upper surface is provided with patterned conductive contacts, while the lower surface is provided with corresponding metal endpoints which are electrically connected with the patterned conductive contacts; secondly, a plurality of welding pads on the active surface of a semiconductor chip are electrically connected with the patterned conductive contacts; thirdly, a packaging body is used for coating the semiconductor and the upper surface of the circuit board; and finally, a plurality of conducting elements are electrically connected with the metal endpoints on the lower surface of the circuit board.

Description

technical field [0001] The invention mainly discloses a semiconductor package structure, more particularly a package structure and method for electrically connecting a semiconductor chip with a conductive contact on a carrier to form a ball grid array. Background technique [0002] In recent years, with the continuous maturity and development of semiconductor technology, various high-performance electronic products are constantly being introduced, and the functions of electronic products are developing towards humanization and multi-function. However, there are various functions inside electronic products. integrated circuit (IC) components. In the production process of electronic components, integrated circuit packaging plays a very important role, and integrated circuit packaging can be roughly divided into dual in-line package (DualIn-line Package, DIP), ball grid array package (Ball Grid Array) package, BGA) and tape automatic bonding (Tape Automatic Bonding, TAB) packa...

AI Technical Summary

Problems solved by technology

However, the above-mentioned existing technologies still use relatively complicated manufacturing procedures, such as: US Patent No. 7,074,696, which discloses a patterned dielectric layer on the substrate, and then the chip is bonded to the dielectric layer. layer (dielectric layer), and make the contacts on the chip between the patterned dielectric layer, after the substrate is removed, the wiring of the metal wire is directly carried out on the patterned dielectric layer

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