Multi-clock system-on-chip with universal clock control modules for transition fault test at speed multi-core

Abstract

A multi-clock system-on-chip (D) comprises i) a core (CE) comprising asynchronous clock domains provided for exchanging test data therebetween, ii) a clock generator unit (CGU) arranged for delivering primary clock signals (clkl-clko) for at least some of the clock domains, and iii) clock control modules (CCl-CCo), arranged respectively for defining the functional clock signals from the primary clock signals and from control signals (intended for setting the clock control modules (CCl) in a normal mode allowing test data transmission from the corresponding emitter clock domain to at least one receiver clock domain or a shift mode forbidding such a test data transmission). Each clock control module (CCl) is connected to a synchronisation means (SM) arranged for switching it from the shift mode to the normal mode, and to a delay means (DM) arranged for putting back the emitter launch edge of a functional clock signal intended for the emitter clock domain when this clock control module (CCl) is set into the normal mode, in order this emitter launch edge be temporally located before each corresponding receiver capture edge of the clock signals intended for the receiver clock domains to which the emitter clock domain must transmit test data.

Description

technical field [0001] The present invention relates to a multi-clock chip-based system that allows real-speed transition failure testing. Background technique [0002] A multi-clock chip-based system of the type described above is a component of an electronic device that typically includes i) at least one core (processor or microcontroller or digital IP) including at least two asynchronous clock domains, the two asynchronous clock domains are provided for exchanging (transmitting and / or receiving) test data between each other, ii) a clock generator unit arranged to supply a master clock signal for at least some of the clock domains, and iii) at least two clock control modules (or blocks), respectively arranged for defining a functional clock signal from said master clock signal and from a control signal. The control signal is designed to set the clock control module into a test normal mode enabling test data transfer from the corresponding sender clock domain to at least o...

AI Technical Summary

Problems solved by technology

Each of these solutions requires additional development time and effort because these blocks are complex (from a timing closure and clock tree construction perspective) and depend on a multi-clock system-on-chip design

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