Effective use of a bht in processor having variable length instruction set execution modes

A technology of execution mode and instruction set, applied in the field of effective organization of branch history table, can solve the problems of increasing cycle time, affecting processor performance, increasing silicon area and power consumption, etc.

Inactive Publication Date: 2009-08-26
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This adds a large number of multiplexers, increasing silicon area and power consumption
More critically, however, it adds delay to the critical path, thereby increasing cycle time and negatively impacting processor performance

Method used

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  • Effective use of a bht in processor having variable length instruction set execution modes
  • Effective use of a bht in processor having variable length instruction set execution modes
  • Effective use of a bht in processor having variable length instruction set execution modes

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Embodiment Construction

[0024] figure 1 A functional block diagram of processor 10 is depicted. Processor 10 includes an instruction unit 12 and one or more execution units 14 . Instruction unit 12 provides centralized control over the flow of instructions to execution unit 14 . The instruction unit 12 fetches instructions from an instruction cache 16 , where memory address translation and permissions are managed by an instruction side translation lookaside buffer (ITLB) 18 .

[0025] The execution unit 14 executes the instructions dispatched by the instruction unit 12 . Execution units 14 read and write general purpose registers (GPR) 20 and access data from data cache 22 , where memory address translation and permissions are managed by main translation lookaside buffer (TLB) 24 . In various embodiments, ITLB 18 may include a replica of portions of TLB 24 . Alternatively, the ITLB 18 and TLB 24 could be integrated. Similarly, in various embodiments of processor 10, instruction cache 16 and data...

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Abstract

In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are formed that access every counter in a branch history table (BHT), and reduce the number of index address bits that are multiplexed based on the current instruction set execution mode. In one embodiment, counters within a BHT line are arranged and indexed in such a manner that half of the BHT can be powered down for each access in one instruction set execution mode.

Description

technical field [0001] The present invention relates generally to the field of processors, and in particular to efficient organization of branch history tables in processors with variable length instruction set execution modes. Background technique [0002] The traditional instruction set architecture of a processor has a uniform instruction length. That is, each instruction in the instruction set includes the same number of bits (eg, 16 or 32). Processors having a variable length instruction set execution mode - wherein the processor can execute instructions having different bit lengths - are known in the art. For example, recent versions of the ARM architecture contain 16-bit instructions executed in a 16-bit instruction set execution mode (Thumb mode) and traditional 32-bit ARM instructions executed in a 32-bit instruction set execution mode (ARM mode). [0003] One problem with processors executing variable length instructions is that the instructions do not fall on un...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/3806G06F9/3844G06F9/30181G06F9/30189G06F9/30149G06F9/06G06F9/30G06F9/32
Inventor 罗德尼·韦恩·史密斯布莱恩·迈克尔·斯坦普尔
Owner QUALCOMM INC
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