Nonvolatile memories with shaped floating gates
By using L-shaped floating gates and alternating directional arrangements in flash EEPROM memory cells, the problem of insufficient coupling between floating gates and control gates is solved, and data density and memory performance are improved.
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[0036] memory structure
[0037] exist figure 1 An example of a memory system 100 incorporating aspects of the present invention is generally illustrated in the block diagram of . The large number of individually addressable memory cells are arranged in a regular array 110 having rows and columns, although other physical arrangements of cells are of course possible. The bit lines designated herein to extend along the columns of cell array 110 are electrically connected to bit line decoder and driver circuit 130 by line 150 . Word lines designated in this description to extend along rows of cell array 110 are electrically connected to word line decoder and driver circuit 190 by line 170 . Each of decoders 130 and 190 receives memory cell addresses from memory controller 180 via bus 160 . The decoder and driver circuits are also connected to the controller 180 via respective control and status signal lines 135 and 195 .
[0038] The controller 180 can be connected to a host ...
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