Nonvolatile memories with shaped floating gates

By using L-shaped floating gates and alternating directional arrangements in flash EEPROM memory cells, the problem of insufficient coupling between floating gates and control gates is solved, and data density and memory performance are improved.

Inactive Publication Date: 2009-09-02
WODEN TECHNOLOGIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Scalability of the flash EEPROM IC system described above can reach similar limits

Method used

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Examples

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Embodiment Construction

[0036] memory structure

[0037] exist figure 1 An example of a memory system 100 incorporating aspects of the present invention is generally illustrated in the block diagram of . The large number of individually addressable memory cells are arranged in a regular array 110 having rows and columns, although other physical arrangements of cells are of course possible. The bit lines designated herein to extend along the columns of cell array 110 are electrically connected to bit line decoder and driver circuit 130 by line 150 . Word lines designated in this description to extend along rows of cell array 110 are electrically connected to word line decoder and driver circuit 190 by line 170 . Each of decoders 130 and 190 receives memory cell addresses from memory controller 180 via bus 160 . The decoder and driver circuits are also connected to the controller 180 via respective control and status signal lines 135 and 195 .

[0038] The controller 180 can be connected to a host ...

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PUM

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Abstract

In a nonvolatile memory using floating gates to store charge, individual floating gates (230) are L-shaped. Orientations of L-shaped floating gates may alternate in the bit line direction and may alsoalternate in the word line direction. L-shaped floating gates are formed by etching conductive portions using etch masks of different patterns to obtain floating gates of different orientations.

Description

technical field [0001] This application relates to non-volatile memory and methods of forming non-volatile memory. In particular, the present application relates to floating gate shaping and different arrangements of shaped floating gates in non-volatile memory. Background technique [0002] There are many commercially successful non-volatile memory products in use today, especially in the form of compact cards, which use arrays of flash EEPROM (Electrically Erasable and Programmable Read-Only Memory) cells. In one type of architecture (NAND array), a series of strings of more than two (eg, 16 or 32) memory cells are connected to each other so that the source of one is also the drain of the other to form a series of cells . Typically, each NAND string composed of, for example, 32 floating gate memory cells in series is terminated with two select transistors, one at each end of the string. The source diffusion of the drain side select transistor is the same as the drain of...

Claims

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Application Information

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Patent Type & AuthorityApplications(China)
IPC IPC(8): H01L21/28H01L21/8247H01L27/115H01L29/423H01L21/3213H10B69/00
CPCH01L27/11521H01L29/42324H01L27/115H01L21/28273H10B69/00H10B41/30H10D64/035H10D30/6891
OwnerWODEN TECHNOLOGIES INC