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Information processing device, memory control method, and memory control device

A technology for information processing devices and control devices, which is applied in memory systems, electrical digital data processing, instruments, etc., can solve the problems that the performance of the devices cannot be improved as expected, and the startup success rate is not high enough, so as to shorten the waiting time and ensure the consistency of the cache Sexuality, the effect of increasing the busy rate

Inactive Publication Date: 2009-09-23
FUJITSU LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0045] As a result, the access initiation success rate is not high enough when the global listen operation is skipped, and the performance of the device may not be improved as desired

Method used

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  • Information processing device, memory control method, and memory control device
  • Information processing device, memory control method, and memory control device
  • Information processing device, memory control method, and memory control device

Examples

Experimental program
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Embodiment Construction

[0072] Embodiments of the present invention will be described below with reference to the drawings.

[0073] An embodiment of the invention

[0074] figure 1 is a block diagram showing the entire configuration of an information processing device as an embodiment of the present invention.

[0075] An information processing device 1 as an embodiment of the present invention is a large-scale SMP information processing device. Such as figure 1 As shown in , the information processing device 1 includes crossbar switches (crossbar switches) XB0 to XB3 ( figure 1 There are four crossbar switches in the example shown in ) and system boards (nodes or memory controllers) SB0 to SB15 (in figure 1 The example shown has 16 system boards). Crossbar switches XB0 to XB3 are connected to system boards SB0 to SB15 so that connections in the entire system are controlled.

[0076] The system boards SB0 to SB15 are separated from each other by partitions (nodes) formed by physical boun...

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Abstract

The present invention provides an information processing device, a memory control method, and a memory control device. In the information processing device that includes nodes (SB0, SB1) each having a main memory (30 to 33) and a processor (10 to 17) including a cache memory (10a to 17a, 10b to 17b), the system controller (50-1, 50-2) of at least one of the nodes (SB0, SB1) is designed to include a holding unit (57-1, 57-2) that holds specific information about primary data present in the main memory (30 to 32) of its subject node (SB0, SB1), with the cache data corresponding to the primary data not present in the cache memory (14a to 17a, 14b to 17b) of the nodes (SB0, SB1) other than its subject node (SB0, SB1). With this structure, the latency of each memory access is shortened, and the throughput of each snoop operation is improved.

Description

technical field [0001] The present invention relates to a technique for executing a memory access request issued from a central processing unit (CPU) of an information processing apparatus including two or more CPUs each having a cache memory. Background technique [0002] In general, a large-scale information processing device (for example, a large-scale SMP (symmetric multiple processor) information processing device) including a plurality of CPUs and input / output (I / O) devices has a system board, each A system board includes a plurality of CPUs with cache memories, a system controller, and a plurality of I / O devices in order to improve processing capabilities. [0003] In such a large-scale information processing apparatus, a control operation is performed to ensure cache coherency among system boards (coherence control operation). Therefore, request broadcast and snoop result exchange are performed between the system controllers of the respective system boards (see, for...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08
CPCG06F12/0822G06F13/10G06F13/16G06F21/30G06F12/00
Inventor 杉崎刚井上爱一郎青木直纯本车田强
Owner FUJITSU LTD
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