Chip data compressing and testing multiplex circuit and chip test circuit

Abstract

The invention discloses a chip data compressing and testing multiplex circuit, wherein a interface circuit can be switched between output units of different compression groups by a multiplexor, multiple groups of compressing and test data can be obtained by utilizing a single interface circuit, thereby effectively raising test speed.

Description

technical field [0001] The invention relates to a chip data compression test multiplexing circuit, in particular to a chip data compression test multiplexing circuit for improving the test output rate. Background technique [0002] An integrated circuit (Integrated Circuit, IC) is small in size and powerful in function, and is one of the indispensable electronic components of information equipment. In order to ensure the normal function of the chip, the chip must be strictly tested before leaving the factory. A simple test method is to input a known test signal to the circuit in the chip, and then obtain a feedback signal from the chip circuit, thereby judging whether the function of the chip is normal. [0003] Figure 1A A schematic diagram of a write portion of a known chip testing circuit 100 is shown. The writing part of the chip testing circuit 100 is connected with a chip testing system (such as a probe card) through the first interface circuit 11 , receives the tes...

AI Technical Summary

Problems solved by technology

In this way, the number of test pins will increase, which will increase the cost of chip testing, and if the test rate of the chip is to be increased, more probes will inevitably be used, resulting in an increase in the overall production cost.

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