Method for test data compression coding and decoding with same run length and special decoding unit

Abstract

The invention relates to a method for test data compression coding and decoding with same run length and a special decoding unit of a large scale integrated circuit, which belong to the technical field of integrated circuit test. In order to reduce the memory capacity of the test data and shorten the testing application time, the invention discloses a method for test data compression coding of the large scale integrated circuit, which comprises the following steps executed by a computer for storing programs: firstly, using a bit string as a basic unit to perform numerical statement on the runs of type 0 and type 1, partitioning the test data, and counting the length of the bit string; secondly, coding the length of the bit string by using two different types of coding modes so that the coding modes not only consider that variable length codes use short code words to replace long original bit strings but also consider the relativity between the runs, and the subsequent runs of continuous runs with the same run length can be further expressed by the short code words so as to achieve the data compression. The decoding method performs decompression by using the decoding unit aiming at the compression method.

Description

1. Technical field [0001] The invention relates to the technical field of integrated circuit testing, in particular to a test data compression method in a built-in self-test (Built-In Self-Test) method for VLSI. 2. Technical background [0002] The development of integrated circuit technology makes it possible to integrate hundreds of millions of devices in a chip, and can integrate pre-designed and verified IP cores, such as memory cores, microprocessor cores, DSP cores, etc. This diversified integrated chip has become an integrated system capable of processing various information, and is called a system on chip or system chip SOC. SOC greatly reduces the system cost, shortens the design cycle, and speeds up the time to market. However, the testing of SOC products faces more and more challenges, such as: [0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the ...

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Problems solved by technology

[0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the limited input / output pins of the chip, and it is difficult to directly control or observe the internal nodes of the chip through macro mechanical devices.

[0004] 2. The automatic test equipment ATE is expensive, and the development speed of chip design and manufacturing technology is faster than that of ATE. The clock frequency of the chip has exceeded the frequency of the most advanced ATE at present, and full-speed testing cannot be performed.

[0005] 3. The amount of test data is large. The more cores integrated in the SOC, the greater the amount of test data required

However, these traditional encoding methods do not consider the correlation between runs, and their compression effects are limited.

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