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Leadless semiconductor package and method of manufacture

A semiconductor and pin technology, which is used in semiconductor/solid-state device manufacturing, semiconductor devices, and semiconductor/solid-state device components, etc., and can solve problems such as affecting reliability, difficulty in bonding lead 124, and reducing pin stability.

Inactive Publication Date: 2012-03-21
UNISEM MAURITIUS HLDG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the reduced thickness of the protrusion reduces the stability of the pin, making bonding of the lead 124 more difficult.
Shear introduces stress into the leads and package, which can affect reliability by causing delamination or microcracks

Method used

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  • Leadless semiconductor package and method of manufacture
  • Leadless semiconductor package and method of manufacture
  • Leadless semiconductor package and method of manufacture

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0025] Figure 4 is a partial perspective view of the frame 10 of the present invention, Figure 5 is its partial cross-section. The frame 10 is formed of a conductive material such as copper or a copper-based alloy. By copper-based it is meant that the alloy contains more than 50% copper by weight. The sawing trace 12 shows the path that the saw blade 22 travels to separate adjacent leadframes 14, 14'. Each lead frame 14 includes pins 16, and pins 16' of adjacent lead frames are interconnected to each other by tie bars 18. As will be described below, the connecting rod 18 is provided with grooves 20 which reduce the amount of metal the saw blade must cut during the singulation process. The topside etch profile may optionally contain an undercut 21 where the pins 16, 16' are connected prior to sawing. This undercut 21 reduces the amount of metal that will be removed during sawing and further minimizes the formation of side burrs.

[0026] Figure 6 shows a bot...

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PUM

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Abstract

A package to encase a semiconductor package is manufactured by the following steps. First, an electrically conductive frame is provided. This frame has a plurality of leadframes arranged in a matrix with each leadframe having a plurality of spaced leads extending outwardly from a central aperture. The electrically conductive frame further includes a plurality of connecting bars joining outer end portions of adjacent ones of the leadframes. Second, a groove is formed in the connecting bars to form a reduced thickness portion between the outer end portions of adjacent ones of the leadframes. Third, a semiconductor device is electrically coupled to inner portions of said leads. Fourth, the frame and the semiconductor devices are encapsulated in a molding compound. Finally, the molding compound and the frame are cut along the grooves to form singulated semiconductor packages having outer lead portions with a height greater than the height of the reduced thickness portion.

Description

technical field [0001] The present invention relates to leadless semiconductor packages and methods of making such packages. More particularly, the present invention relates to methods of manufacturing leadless semiconductor packages with reduced lead burr and improved solder fillet. Background technique [0002] Semiconductor device packaging provides environmental protection for one or more integrated circuit devices, known as semi conductor die, enclosed within the package. The semiconductor die has input / output (I / O) pads that are electrically interconnected by wire bonds, tape bonds, etc. to inner pin portions of a leadframe or interposer. Opposite outer lead portions of the leadframe or interposer are electrically interconnected to circuitry on a printed circuit board, flex circuit, or other external circuitry. A polymer molding resin encloses the semiconductor die and the lead frame or at least the inner lead portion of the interposer. [0003] When the outer lead ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60
CPCH01L2224/45124H01L2924/01046H01L2924/01082H01L2224/97H01L2224/32245H01L21/568H01L24/50H01L2924/01029H01L2924/01028H01L2224/16245H01L2224/48091H01L2924/01013H01L2924/014H01L2224/92247H01L24/97H01L2224/92H01L24/45H01L2924/01047H01L24/48H01L2924/01079H01L2224/48247H01L2924/14H01L23/49548H01L2924/01005H01L2924/01033H01L2924/01006H01L23/3107H01L2924/01078H01L2224/48257H01L2924/01058H01L2224/45144H01L2224/73265H01L2224/85001H01L21/561H01L24/73H01L24/86H01L2224/45015H01L2924/181H01L2924/00014H01L2224/85H01L2224/83H01L2924/00012H01L2924/00
Inventor R·S·圣安东尼奥A·苏巴迪奥
Owner UNISEM MAURITIUS HLDG