Method and device for processing abnormity of PCI system

Abstract

The invention relates to a method and a device for processing the abnormity of a peripheral component interconnect (PCI) system. An abnormity monitoring and isolating device arranged between host equipment in the PCI system and PCI equipment implements the following steps: A. monitoring the access of the host equipment to the PCI equipment used as target equipment through a PCI bus; B. isolating the accessed target equipment when monitoring that abnormity occurs in access; and C. replacing the accessed target equipment to send a target abolition response to the host equipment when the isolated target equipment is accessed. The invention can prevent the whole PCI system from collapsing probably caused by the long-time occupation of the PCI bus, enhance the reliability of the PCI system and reduce the performance loss of the system when the PCI equipment has abnormity to the maximum extent.

Description

technical field [0001] The present invention relates to the technical field of network communication, and in particular, to a method and device for handling abnormality of a PCI system. Background technique [0002] Peripheral Component Interconnect (PCI, Peripheral Component Interconnect) bus is widely used because of its advantages of open architecture, ease of use and good scalability. figure 1 It is a schematic diagram of the structure of a PCI system. The host device is the built-in PCI controller of the CPU, which is usually also called the PCI host bridge controller. In the PCI system, multiple PCI devices can be connected through the PCI bus, and the PCI device can be a fixed device. It can also be a plug-in device, a bootstrap device or a common device. After the host device is powered on, it first completes its basic configuration, scans each PCI device through the PCI bus, and configures each PCI device accordingly. After the configuration is complete, the host d...

AI Technical Summary

Problems solved by technology

[0003] In the PCI system, if a piece of PCI equipment fails when it is used as the target device, it may cause the failure of the entire PCI system and cannot work normally. For example, the following problems may occur: First, when the master device accesses the target device, the target device fails Causes delay in getting ready for data reception after declaring the transaction, that is, after sending a valid DEVSEL signal in the third clock cycle, it does not send a valid TRDY signal in the fourth cycle and later, so that the host device has been waiting At the same time, the target device cannot send a retry or transaction abolition signal, which will cause the PCI system to be monopolized by this transaction for a long time, and the bus will hang.

Second, if the target device is a bootstrap device, it does not rely on the configuration of the host device after power-on, but performs initial configuration by itself. Before the target device completes the initial configuration, it is in a locked (Locked) state, and the host device cannot access, access transactions to it will be retried

If the bootstrap device is abnormal during the initialization process and cannot complete the initialization configuration, the host device's access to it will be retried indefinitely, causing the bus to be occupied for a long time

In addition, there may be other abnormal conditions that cause the bus to be occupied for a long time, resulting in the collapse of the entire PCI system.

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