Stacked type chip package structure

Abstract

The invention provides a chip package structure and a stacked type chip package structure. The stacked type chip package structure employs a substrate having a pseudo-cavity or a keep-out zone at oneside or both sides thereof. Through the pattern arrangement of the wiring layer and the solder mask layer, the thickness of the entire stacked type chip package structure is effectively reduced as lower wire loops and a thinner mold-cap can be achieved by mounting the chip within the depressed keep-out zone. In particular, the double-sided chip package structures are suitable for package on package structures adopted by mobile applications.

Description

technical field [0001] The present invention relates to a multi-chip packaging structure, and in particular to a chip packaging structure and a stacked chip packaging structure. Background technique [0002] Multi-chip package (Multiple-chip package, MCP) is generally used in various applications requiring high power, low energy consumption and small size. In fact, mobile or portable products need to use a relatively thin package structure with multiple functions. [0003] The prior art adopts a packaging substrate (recessed substrate) having a recess to receive a chip through the recess. Such as figure 1 As shown, a chip packaging structure 10 with a recess 102 in the prior art mainly includes a carrier 100 , a chip 110 , a plurality of wires 120 and an encapsulant 130 . The recess 102 of the carrier 100 can accommodate the chip 110 , and the chip 110 is electrically connected to the pad 106 of the carrier 100 through a plurality of wires 120 . The encapsulant 130 cover...

AI Technical Summary

Problems solved by technology

Double-sided chip package structure is quite useful for package-on-package

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