Electronic package and manufacturing method thereof

Abstract

The invention provides an electronic package, which comprises at least a first module and a second module arranged at the top of the first module, wherein the modules are combined together to form a module stack; the first and the second modules are adhered together; each module comprises a substrate layer comprising at least one metal layer, at least one wafer and a plastic packaging mold compound layer; the wafer in each module is bonded on the substrate layer by the metal layer; multiple channels which are formed vertically are used as through holes to connect with the metal layer and are near the wafer in at least one module; the inner surfaces of some or all the channels are coated with conducting material layers or filled with the conducting materials so as to perform electrical connection; and thereby the wafers are electrically connected together, are used as a medium device for providing electrical, mechanical and thermal connection for outer communication, and are connected with the channels.

Description

technical field [0001] The invention relates to an electronic package, an electronic package component and a manufacturing method thereof. Background technique [0002] Electronic packages that include multiple chips are not new. Electronic packages can be divided into different categories. For example, some electronic packages in the prior art are classified into (including but not limited to) (i) wire-bonded (WB) wafer stacks, (ii) package-on-packages (PoP), and (iii) through-silicon vias (TSV) . While these various types of electronic packaging offer advantages in some respects, they are often deficient in others. For example, although WB die stacking is considered to be a relatively simple structural concept and a mature technology, its signal performance (due to the need to use a large number of external lead connections), size and testability are often unsatisfactory. Also, WB die stacking often results in large packages, which are not allowed in the small electron...

AI Technical Summary

Problems solved by technology

For example, although WB die stacking is considered a relatively simple structural concept and a mature technology, its signal performance (due to the need to use a large number of external lead connections), size and testability are often unsatisfactory

Also, WB die stacking often results in large packages, which are not allowed in the small electronics environment

PoP may have better testability, but its electrical performance and size are also not satisfactory

Chip stack packages based on TSVs in the prior art have better electrical performance and size, but they have poor testability and high manufacturing cost due to manufacturing complexity

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