Method of driving a semiconductor memory device and a semiconductor memory device
A memory and semiconductor technology, applied in the direction of semiconductor devices, static memory, digital memory information, etc., can solve problems such as hindering read or write operations and increasing power consumption
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no. 1 example
[0073] figure 1 is a schematic diagram showing an example of the configuration of the FBC memory device according to the first embodiment of the present invention. The FBC memory device 100 includes a memory cell MC, word lines WLL0 to WLL255 and WLR0 to WLR255 (hereinafter, also referred to as “WL”, “WLL” or “WLR”), bit lines BLL0 to BLL1023 and BLR0 to BLR1023 (hereinafter, Herein, also referred to as "BL", "BLL" or "BLR"), sense amplifier S / A, source line SL, row decoder RD, word line driver WLD, column decoder CD, sense amplifier controller SAC and DQ buffer DQB.
[0074] The memory cells MC are two-dimensionally arranged in a matrix, which constitutes memory cell arrays MCAL and MCAR (hereinafter, also referred to as "MCA"). Each word line WL extends in the row direction and is connected to the gate of each memory cell MC. 256 word lines WL are arranged on both the left and right sides of the sense amplifier S / A. Each bit line BL extends in the column direction and is...
no. 2 example
[0115] Figure 8 is an explanatory diagram showing a method of driving an FBC memory device according to a second embodiment of the present invention. The second embodiment differs from the first embodiment in the second cycle. Since the first cycle according to the second embodiment is the same as that according to the first embodiment, it will not be described here.
[0116] In the second loop according to the second embodiment, holes are extracted from the selected memory cell MC00 among the memory cells MC00 and MC10 connected to the selected word line WL0. Data "0" is thereby written into the selected memory cell MC00. A small amount of holes are extracted from an unselected memory cell MC10 among the memory cells MC00 and MC10 connected to the selected word line WL0 . The data "1" is thereby written into the unselected memory cell MC10.
[0117] In the second cycle, the potential of the selected word line WL0 is biased to have the same polarity as that of the majorit...
no. 3 example
[0125] Figure 11 is a plan view showing wiring arrangements in the FBC memory device according to the third embodiment of the present invention. The bit lines BL extend in the column direction. Word lines WL and source lines SL extend in a row direction orthogonal to bit lines BL. Memory cells MC are provided at intersections of bit lines BL and word lines WL, respectively. Each bit line BL is connected to the drain D of each memory cell MC by a bit line contact BLC. The word line WL also serves as the gate electrode G of each memory cell MC. Each source line SL is connected to the source S of each memory cell MC by a source line contact SLC.
[0126] Considering the position deviation between the bit line contact BLC and the source line contact SLC, the margin between one word line WL and one bit line contact BLC and the margin between one word line WL and one source line contact SLC The margin is set as the distance D. According to the progress of technology, the dist...
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