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Self-correction precursor 0/1 predicting unit for floating-point adder

A prediction unit and adder technology, applied in the direction of instruments, electrical digital data processing, digital data processing components, etc., can solve the problems of counting error, leading 0 prediction unit inaccuracy, etc.

Inactive Publication Date: 2010-04-28
XI AN JIAOTONG UNIV
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Problems solved by technology

[0034] The aforementioned leading 0 prediction unit is imprecise: a one-bit error may occur when counting

Method used

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  • Self-correction precursor 0/1 predicting unit for floating-point adder
  • Self-correction precursor 0/1 predicting unit for floating-point adder
  • Self-correction precursor 0/1 predicting unit for floating-point adder

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Embodiment Construction

[0085] The present invention will be described in further detail below in conjunction with the accompanying drawings.

[0086] see figure 1, used for the self-correcting leading 0 / 1 prediction unit of the floating-point adder, for the addition operation of two specific numbers, the T, G, Z signals can be obtained by bitwise processing, and then T, G, The leading 0, 1 prediction can be realized by processing the Z three signals. Due to the combination of leading 0 and 1 prediction units, the hardware structure will inevitably be complicated, and the critical path will become longer, which is not conducive to improving the speed. Therefore, in the design of the present invention, the method of separating the leading 0 prediction unit and the leading 1 prediction unit is adopted, and the following two formulas are respectively used to calculate f i :

[0087] f i =T i ·Z i+1 , i≥0 (15)

[0088] f i =T i ·G i+1 , i≥0 (16)

[0089] Among them, formula (15) is the calcula...

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Abstract

The invention relates to a self-correction precursor 0 / 1 predicting method for a floating-point adder, which adopts the combination method of a multiple-input logical gate and parallel computation to realize an output result as a final correct result, and the output result has no need to be corrected by depending on an adder; the parallel computation is adopted, for example, the operand bit wide is increased, and the critical path length can not be influenced. When the floating-point add is computed, the displacement time and index regulating information needed by the normalization of a computation result is synchronously predicted, a predicting result is not output by the adder but is generated by the predicting unit and is a corrected value which has no need to be further corrected, and the critical path of the predicting unit can not be lengthened along with lengthening the bit wide of an operand.

Description

technical field [0001] The invention relates to a leading 0 / 1 prediction method, in particular to a self-correcting leading 0 / 1 prediction method for a floating-point adder. Background technique [0002] The document "G. Zhang, W. Hu, Z. Qi, "Parallel error detection for leading zero anticipation". Journal of Computer Science and Technology, v 21, n 6, p 901-906, November 2006." proposed a parallel The leading 0, 1 prediction unit error correction technology that can realize error correction without relying on the carry signal of the adder is realized. The main idea is to use "positive tree" and "negative tree" to compress the results of "positive encoding" and "negative encoding", and finally output the correct result through OR logic. Its unique tree-like compression structure makes the "encoding" signal have to pass through a series of logic gates before finally reaching the output terminal. In this hierarchical tree-like structure, the length of the key path is determin...

Claims

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Application Information

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IPC IPC(8): G06F7/575
Inventor 邵志标李凌浩王丽
Owner XI AN JIAOTONG UNIV
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